Did You Know...
...that after Parker Brothers executives turned down the game of Monopoly because it had "52 fundamental errors" (including taking too long to play), a copy of the game wound up in the home of the company president who stayed up until 1 a.m. to finish playing it? He was so impressed by the game that the next day he wrote to inventor Charles Darrow and offered to buy it!
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| Number | Title | Issue Date |
| 8283984 | Method and apparatus of phase locking for reducing clock jitter due to charge leakage A phase lock loop is disclosed comprising a first phase detector configured to receive a first clock and a second clock and output a first detector output signal; a second phase detector configured to receive the first clock and the second clock and output a second ... | 10/09/2012 |
| 8207792 | Phase locked loop and phase-frequency detector The phase-frequency detector (PFD) includes a frequency detector (FD) arranged to receive orthogonal signal pairs of a reference signal and a feedback signal and estimate a frequency error between a reference signal and a feedback signal; a FD voltage-to-current con... | 06/26/2012 |
| 8138841 | Apparatus and method for controlling the output phase of a VCO A method and apparatus controlling the output phase of a VCO (Voltage Controlled Oscillator). The apparatus has a phase locked loop 20 having a first input 21 for receiving a reference signal and a second input 22 for receiving a feedback signal... | 03/20/2012 |
| 8111106 | Switched phase and frequency detector based DPLL circuit with excellent wander and jitter performance and fast frequency acquisition Some embodiments of the present invention may include a DPLL circuit comprising a firmware. The firmware may comprise a re-sampled NCO phase detector capable of receiving a reference clock timing signal and a VCXO clock timing signal. The re-sampled NCO phase detect... | 02/07/2012 |
| 8063707 | Phase locked loop Phase locked loop circuits capable of increasing an equivalent capacitance thereof to improve stability are provided, in which an integral part comprises a first phase frequency detector providing a phase error signal, a first charge pump circuit generating a contro... | 11/22/2011 |
| 7936222 | Phase-locked loop circuit employing capacitance multiplication A phase-locked loop circuit. The phase-locked loop circuit comprises a phase detector, a proportional charge pump, a decimator, an integral charge pimp, and a voltage-controlled oscillator. The phase detector obtains an phase error information according to a phase d... | 05/03/2011 |
| 7825737 | Apparatus for low-jitter frequency and phase locked loop and associated methods A frequency phase locked loop (FPLL) includes a first feedback loop coupled to a second feedback loop. The first feedback loop is configured to correct a phase offset of an output signal of the FPLL. The second feedback loop is configured to correct a frequency offs... | 11/02/2010 |
| RE41235 | Phase locked loop circuit A PLL circuit comprises a frequency comparator for detecting a phase difference based on a difference in frequencies between a reproduced data pulse and a clock generated by a VCO; a phase comparator for detecting a difference in phases between the reproduced data p... | 04/20/2010 |
| 7692496 | Method and apparatus for generating output signal The oscillating signal generator utilizes a rising edge phase difference and a falling edge phase difference of the input signal and a feedback signal to generate a rising control signal and a falling control signal, and generates an output signal according to the r... | 04/06/2010 |
| 7679454 | Hybrid phase-locked loop A phase-locked loop (PLL) including a digital PFD, a digital loop filter, a decision circuit, a fractional-N PLL, and a frequency divider is provided. The digital PFD generates a first detection signal according to the phase error or frequency difference between an ... | 03/16/2010 |
| 7642861 | Locked loop system This disclosure relates to a phase locked loop and a frequency locked loop. ... | 01/05/2010 |
| 7622996 | Multi-loop phase locked loop circuit Disclosed is a multi-loop PLL circuit and a related method of which, the circuit includes: a first loop for generating a first control current; a second loop for generating a second control current; a loop filter for generating a control signal according to the firs... | 11/24/2009 |
| 7605662 | Oscillator controller incorporating a voltage-controlled oscillator that outputs an oscillation signal at a desired oscillation frequency An oscillator controller has a phase frequency detector that compares a reference signal and a frequency-divided signal and outputs a phase difference signal; a charge pump; a loop filter that filters the phase error signal output from the charge pump and outputs an... | 10/20/2009 |
| 7564313 | Phase locked loop for controlling a recording device and method thereof A PLL system for generating an output signal according to a first reference signal is disclosed. The PLL system includes a clock generator to generate the output signal according to a phase difference between the first reference signal and the frequency-divided sign... | 07/21/2009 |
| 7554412 | Phase-locked loop circuit having correction for active filter offset A phase locked loop (PLL) circuit automatically corrects the offset of the analog (especially active type) loop filter to improve the stability and precision of the locked clock or frequency signals. In addition to the general PLL circuit configuration having active... | 06/30/2009 |
| 7548121 | Fractional frequency synthesizer and phase locked loop utilizing fractional frequency synthesizer and method thereof A fractional frequency synthesizer, applied to a phase-locked loop, includes a phase detector, a loop filter, a controllable oscillator, a first frequency divider, and a sigma-delta modulator (SDM). The phase detector generates a phase difference signal according to... | 06/16/2009 |
| 7443250 | Programmable phase-locked loop responsive to a selected bandwidth and a selected reference clock signal frequency to adjust circuit characteristics A technique that is readily implemented in monolithic integrated circuits includes a phase-locked loop (PLL) that generates an output clock signal based on a reference clock signal and selectable configuration parameters. A method includes providing to a PLL circuit... | 10/28/2008 |
| 7443247 | Circuit arrangement for detection of a locking condition for a phase locked loop, and a method A circuit arrangement includes a phase locked loop, having a phase detector on whose output side a phase signal can be tapped off and whose output side is coupled to a charge pump. Furthermore, the phase locked loop includes an oscillator whose input side is coupled... | 10/28/2008 |
| 7439816 | Phase-locked loop fast lock circuit and method Phase-locked loop fast lock circuit and method are described. The apparatus including a voltage controlled oscillator, a control loop filter having a capacitor and at least one resistor, and first and second control elements coupled with the control loop filter. The... | 10/21/2008 |
| 7439812 | Auto-ranging phase-locked loop A phase locked loop circuit includes an oscillator, a dividing circuit coupled to the oscillator having a controllable dividing factor, and a rangefinder circuit coupled to the dividing circuit. The rangefinder circuit is configured to control the dividing factor in... | 10/21/2008 |
| 7436264 | Charge supply apparatus and method in frequency synthesizer A charge supplying apparatus in a frequency synthesizer includes first and second charge supply units. The first charge supply unit is activated for generating a first voltage coupled to a loop filter, and the second charge supply unit is activated for generating a ... | 10/14/2008 |
| 7427899 | Apparatus and method for operating a variable segment oscillator This disclosure is directed to a communications device having a comparator that receives a signal associated with an output and produces a signal associated with a difference between a reference signal and the output signal. A loop filter is coupled to the comparato... | 09/23/2008 |
| 7405628 | Technique for switching between input clocks in a phase-locked loop A technique that is readily implemented in monolithic integrated circuits reduces or eliminates phase glitches when switching between input reference clock signals. The technique combines a pulsed phase-difference signal and a pulsed phase-difference compensation si... | 07/29/2008 |
| 7397312 | Spectrum analyzer and method for correcting frequency errors A spectrum analyzer corrects for internal frequency errors in a reference oscillator using a timing control signal. The reference oscillator provides a reference signal at a reference frequency. An error detection circuit determines an error in the reference frequen... | 07/08/2008 |
| 7389192 | Determining data signal jitter via asynchronous sampling A method for determining data signal jitter via asynchronous sampling provides a low cost and production-integrable mechanism for measuring data signal jitter. The data signal is edge-detected and sampled by a sampling clock of unrelated frequency the sampled values... | 06/17/2008 |
| 7388437 | System and method for tuning a frequency synthesizer An apparatus for generating an output signal having a particular frequency includes an oscillator, a first tuning module, and a second tuning module. The oscillator generates an output signal associated with an output frequency. When coupled to the oscillator, the f... | 06/17/2008 |
| 7383160 | Method and apparatus for constructing a synchronous signal diagram from asynchronously sampled data A method a low cost and production-integrable technique for providing a signal diagram. The data signal is edge-detected and asynchronously sampled (or alternatively a clock signal is latched). The data signal or a second signal is compared to a settable threshold v... | 06/03/2008 |
| 7373575 | Method and apparatus for generating expect data from a captured bit pattern, and memory device using same Expect data signals are generated for a series of applied data signals having a known sequence to determine if groups of the data signals were properly captured. A first group of the applied data signals is captured, and a group of expect data signals are generated ... | 05/13/2008 |
| 7372339 | Phase lock loop indicator A phase-locked loop (PLL) circuit includes a power-on-reset (POR) to reset a digital block and set an initial input voltage value VCTRL of voltage-controlled oscillator (VCO). An input divider and a feedback divider are provided to set the frequency ratio of output ... | 05/13/2008 |
| 7365593 | Output equalized charge pump A charge pump circuit has a charge pump section and a replica charge pump section. The replica charge pump section produces a replica voltage at which the UP current will match the DOWN current. A comparator compares the replica voltage to the output voltage, and ad... | 04/29/2008 |
| 7362185 | Analog based, state machine controlled, frequency smooth switching method for frequency timing generators A method and circuit for performing switching in a frequency timing generator is described. The method includes detecting a request for a new value for a feedback counter or an reference counter, upon which a loading operation is synchronized for the appropriate cou... | 04/22/2008 |
| 7362184 | Frequency divider monitor of phase lock loop A circuit and method for monitoring a frequency divider. The circuit including a phase locked loop circuit including a voltage controlled oscillator and a feedback frequency divider, an output of the voltage controlled oscillator connected to an input of the feedbac... | 04/22/2008 |
| 7362826 | Receiver including an oscillation circuit for generating an image rejection calibration tone A receiver circuit includes an oscillator circuit configured to generate a calibration tone and a phase locked loop (PLL) reference signal. An output frequency of the VCO may be divided by respective amounts to derive a desired calibration tone frequency and a desir... | 04/22/2008 |
| 7356111 | Apparatus and method for fractional frequency division using multi-phase output VCO A phase-locked loop (PLL) frequency synthesizer capable of being tuned in small step sizes. The PLL frequency synthesizer includes a PLL circuit. A phase-locked loop (PLL) frequency synthesizer includes a PLL core and a feedback frequency divider. The PLL core recei... | 04/08/2008 |
| 7356423 | Apparatus and method for reading out a differential capacity with a first and second partial capacity An apparatus for reading out a differential capacity with a first and second partial capacity includes a first oscillator having a first frequency-determining element connectable to the first partial capacity and a second oscillator having a second frequency-determi... | 04/08/2008 |
| 7355490 | Receiver having no tracking error A receiver includes an up/down counter that controls turning on/off of individual switching units, and a count signal generator that compares a control voltage with a first reference voltage and a second reference voltage lower than the first reference voltage and o... | 04/08/2008 |
| 7355482 | Methods and apparatus for compensating a variable oscillator for process, voltage, and temperature variations using a replica oscillator Circuits and methods for compensating a variable oscillator for process and/or operational variations. The circuit generally comprises (a) a replica oscillator, (b) a counter configured to count pulses of the replica oscillator and to produce a count signal, and (c)... | 04/08/2008 |
| 7355462 | Phase lock loop and method for operating the same A digital controller for a voltage controlled oscillator (VCO) is provided within a phase lock loop (PLL). The digital controller includes a digital filter having first and second inputs for receiving upward and downward adjustment signals, respectively. The digital... | 04/08/2008 |
| 7352837 | Digital phase-locked loop A phase-locked loop includes a variable frequency generator, a comparator and a counter. The variable frequency generator is configurable for generating an output signal having a frequency which varies based at least in part on at least first and second control sign... | 04/01/2008 |
| 7352248 | Method and apparatus for maintaining a clock/data recovery circuit frequency during transmitter low power mode A method, algorithm, software, architecture, circuit, and/or system for detecting an idle condition and maintaining a frequency of a clock/data recovery circuit are disclosed. In one embodiment, a method of maintaining a frequency of a clock/data recovery circuit ca... | 04/01/2008 |
