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| Number | Title | Issue Date |
| 8159288 | Low power BPSK demodulator A low power BPSK demodulator having a simple architecture, compact design and reliable is provided. The BPSK demodulator includes a first branch (210) having a first mixer (212) and a first low pass filter (214), a second branch (220) cou... | 04/17/2012 |
| 8081027 | Reception device, control method, and program A reception device that receives a modulation signal being a result of digital modulation of a carrier is disclosed. The device includes: a demodulation section that demodulates the modulation signal into a demodulation signal incl... | 12/20/2011 |
| 7728657 | PLL circuit, phase shifting method, and IC chip A Phased Locked Loop (PLL) circuit includes: a clock signal generating unit for generating a first clock signal and a second clock signal of which the phase differs from the first clock signal by Î /2; a computing unit for computing first phase comparison results sh... | 06/01/2010 |
| 7362255 | Chopping and oversampling ADC having reduced low frequency drift An integrated circuit includes an analog-to-digital (ADC) portion and a processor portion. The processor portion generates high frequency noise. The ADC portion includes chopper switches, an ADC, a first low-pass filter (LPF), an inverter, and a second LPF. An analo... | 04/22/2008 |
| 7359459 | System and method for low power clear channel assessment A method is provided for performing a clear channel assessment in a local device. The local device receives signal energy in a wireless channel and splits the received signal energy into a real portion and an imaginary portion. It determines a real portion of a squa... | 04/15/2008 |
| 7359460 | Coherent and non-coherent data path splitting in receivers for improved synchronization An improved data communication receiver technique is provided which avoids demodulation errors due to abrupt phase changes. A receiver is provided for processing an incoming digitized signal. The receiver comprises a pre-processing portion, a phase error correction ... | 04/15/2008 |
| 7356077 | Method and apparatus for testing network integrity Apparatuses and methods for testing the integrity of high speed optical fiber transmission networks are presented. Data from an optical network, for example, NRZ formatted data at forty gigabits per second and higher may be reliably recovered using embodiments of th... | 04/08/2008 |
| 7342986 | Digital PLL device A phase-locked-loop device includes a clock generator for generating a reference clock based on a binarized playback signal and a frequency of run-length data and for generating N-phase clocks using the reference clock, a pulse-length measuring device for measuring ... | 03/11/2008 |
| 7336732 | Carrier frequency detection for signal acquisition A carrier frequency in a filtered received M-ary phase-shift keyed (MPSK) modulated signal having in-phase and quadrature components is detected by processing the filtered received signal to remove modulation components and thereby generate a test signal at the carr... | 02/26/2008 |
| 7302011 | Quadrature frequency doubling system The frequency doubler of the present invention operates to provide an in-phase signal and a quadrature signal, each having a frequency equal to twice the frequency of a reference signal. The in-phase and quadrature signals are based on signals that are 0 degrees, 45... | 11/27/2007 |
| 7280615 | Method for making a clear channel assessment in a wireless network A method is provided for performing a clear channel assessment in a wireless network. The method involves first listening for channel energy on a wireless channel. Whatever channel energy is heard over the wireless channel is demodulated into non-synchronized in-pha... | 10/09/2007 |
| 7277502 | Carrier recovery apparatus A carrier recovery apparatus capable of detecting a phase error of modulation signal by a simple calculation, reducing the circuit scale, and improving the frequency capture characteristic and phase jitter characteristic is presented. This carrier recovery apparatus... | 10/02/2007 |
| 7263139 | Phase correction for a phase modulated signal with mutually interfering symbols A circuit and method for correcting phase of a received phase modulated (PM) signal. The method uses k most recently received data bits, which alternate between in-phase I and quadrature Q bits, as an address for a lookup table 60. The lookup table outputs a ... | 08/28/2007 |
| 7248664 | Timesliced discrete-time phase locked loop A time-sliced discrete-time Phase Locked Loop which is suitable for simultaneously synchronizing multiple input signals to multiple output signals is provided by implementing a discrete-time phase detector, loop filter, and voltage controlled oscillator that togethe... | 07/24/2007 |
| 7239666 | Communication system A communication system that can satisfactorily communicate with a mobile station by a transmitter and receiver of a simple arrangement wherein a plurality of carriers having different frequencies are transmitted simultaneously and data is transmitted on the basis of... | 07/03/2007 |
| 7239431 | System and method for recovering primary channel operation in a facsimile receiver and facsimile machine incorporating the same A system for, and method of recovering primary channel operation in a facsimile (fax) receiver and a fax machine that incorporates the system, the method or both. In one embodiment, the system includes: (1) a signal receiver that receives a signal containing first a... | 07/03/2007 |
| 7233632 | Symbol timing correction for a phase modulated signal with mutually interfering symbols A circuit and method for correcting timing of a received phase modulated signal. The method uses k most recently received data bits as an address for a lookup table 60. The lookup table includes reconstructed waveforms from which a timing weighing factor is d... | 06/19/2007 |
| 7197136 | Digital portable telephone set Phase data 129 of received signal is fed through a one symbol delaying unit 141 and a second substracter 1 to a second decoder 2 for decoding to generate quality data 133c. The quality data 133c is computationa... | 03/27/2007 |
| 7187727 | Clock and data recovery circuit and clock control method To provide a clock and data recovery circuit which facilitates alteration of the frequency range and adjustment of characteristics. The clock and data recovery circuit includes a phase shift circuit 101 having a switch receiving as inputs multi-phase clocks f... | 03/06/2007 |
| 7158772 | Filter for broadcast receiver tuner A Gaussian family filter (e.g. an equiripple filter) comprises a first pole, a second pole, a third pole and a signal combiner. The first pole has a biquadratic low pass characteristic and is configured to provide a first low pass signal. The second pole is coupled ... | 01/02/2007 |
| 7158566 | High-speed adaptive interconnect architecture with nonlinear error functions A low cost and high speed equalizing receiver structure is provided for improved inter-chip and inter-module communications. The receiver is able to recover data from a corrupted waveform from a signal wire such as one found on data, address or control wires in a mi... | 01/02/2007 |
| 7145894 | Continuously adjusted-bandwidth discrete-time phase-locked loop A user equipment which receives a CDMA communication signal that is wirelessly transmitted includes a system for correcting phase errors in an information signal which has been transmitted. The correction system comprises circuitry for generating a correction signal... | 12/05/2006 |
| 7142622 | Multiplying phase detector for use in a random data locked loop architecture A multiplying phase detector includes a 1st multiplier, a 2nd multiplier and a phase error generation module. The 1st multiplier is operably coupled to multiple an incoming data stream, which is a random data pattern, with a 1st... | 11/28/2006 |
| 7136440 | Timing recovery for data sampling of a detector A partial response Class 4 detector in a recording and retrieval system and method of operating the detector for correcting the timing error of the detector. The detector includes a sequence table and comparison circuitry for comparing a sequence of data samp... | 11/14/2006 |
| 7113047 | Clock generator and its control method To present a clock generator capable of spreading the spectrum of oscillation frequency by simple control in a small additional circuit, and its control method. A phase locked loop circuit is provided from a frequency phase comparator 11, an output clock sign... | 09/26/2006 |
| 7072783 | Frequency and timing error estimation and corresponding channel characterization in a communication system A method for determining a frequency error over at least one frequency search space for a received signal, the method including the steps of: calculating a first noise estimation for a first frequency offset in a frequency search space; calculating at least a second... | 07/04/2006 |
| 7054778 | Method and device for processing analogue output signals from capacitive sensors An analogue output signal of a sensor which comprises a carrier signal with a carrier frequency ωC which is modulated by a measurement size is sampled with a sampling frequency ωA to receive a sampled sensor output signal. The frequency ω | 05/30/2006 |
| 7003016 | Maximum likelihood timing synchronizers for sampled PSK burst TDMA system A method of producing a correction signal includes receiving a predetermined data sequence (500). The data sequence is sampled at predetermined times, thereby producing a sampled data sequence (522, 532). The sampled data sequence is separated into fir... | 02/21/2006 |
| RE38876 | System for, and method of, processing quadrature amplitude modulated signals Analog signals encoded with quadrature amplitude modulation (QAM) pass through a coaxial cable at a particular baud rate. These signals have a carrier frequency individual to the TV station being received. They are mixed with signals from a variable frequency oscill... | 11/15/2005 |
| 6956908 | Technique to simultaneously distribute clock signals and data on integrated circuits, interposers, and circuit boards A technique is described for simultaneously and synchronously transmitting digital data and a clock signal in a digital integrated circuit, circuit board, or system. The technique is based on the phase shift keying (PSK) modulation of an RF high frequency carrier wh... | 10/18/2005 |
| 6954472 | Method and device of superimposing an additional information signal on a video signal and detecting said additional information from said video signal A method of superimposing additional information on a video signal, transmitting it, and detecting the additional information from the transmitted video signal. The additional information is synchronized with a sync signal in the video signal, and generated in N (Nâ... | 10/11/2005 |
| 6952239 | Sine generation circuit, phase shift circuit and tint adjustment circuit A phase shift circuit includes a first sine generation circuit generating a sine-converted output signal (sin θ) of the phase shift input signal (θ) and a reversed sine-converted output signal (−sin θ) of the phase shift input signal (θ), a cosine generation c... | 10/04/2005 |
| 6940875 | Continuously adjusted-bandwidth discrete-time phase-locked loop A reciever for receiving a CDMA communication signal that is wirelessly transmitted includes a system for correcting phase errors in an information signal which has been transmitted. The correction system comprises circuitry for generating a mixing signal and for co... | 09/06/2005 |
| 6940923 | Demodulating device, broadcasting system, and semiconductor device A demodulating device capable of high-efficiency, high-accuracy phase noise correction control and improved in quality and reliability. A digital signal generating portion synchronously detects a modulated input signal and subjects the signal to A/D conversion to ge... | 09/06/2005 |
| 6915081 | PLL circuit and optical communication reception apparatus The invention provides a PLL circuit wherein, even if the duty ratio of an input signal varies, stabilized PLL operation is achieved. The PLL circuit includes a phase detection circuit and a frequency detection circuit. The frequency detection circuit includes a pai... | 07/05/2005 |
| 6909388 | Fractal sequencing schemes for offset cancellation in sampled data acquisition systems The present invention is directed to the isolation and cancellation of the offset voltage component typically experienced at the input of sampled-data analog systems. In an exemplary embodiment, offset isolation and cancellation may be performed during normal operat... | 06/21/2005 |
| 6903531 | Circuit for driving a stepper motor and method of controlling a stepper motor driver A driver circuit is provided for a stepper motor which utilizes a processor that outputs a PWM signal. The driver circuit includes an H-bridge circuit having first and second inputs, and a switching circuit having an input and an output. The first H-bridge input and... | 06/07/2005 |
| 6861900 | Fast timing acquisition for multiple radio terminals A method and apparatus are provided that performs timing acquisition for multiple radio terminals. According to one aspect of the present invention the invention includes receiving a sequence of symbols modulated onto a carrier frequency over a channel and demodulat... | 03/01/2005 |
| 6781447 | Multi-pass phase tracking loop with rewind of current waveform in digital communication systems A demodulator demodulates a modulated signal waveform in a data communication system. A phase tracking loop tracks the phase of said modulated signal waveform and having an inner block decoder configured to decode a set of vector pairs of the modulated signal wavefo... | 08/24/2004 |
| 6731698 | Quadrature demodulation circuit capable for canceling offset When a clock reproduction circuit (6) is locked, a phase comparator (9) detects a level difference ΔE between a zero crossing point and a true 0 level. The level difference ΔE represents an offset level and is output as an offset detection signal. Af... | 05/04/2004 |
