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| Number | Title | Issue Date |
| 8086989 | Structure for glitchless clock multiplexer optimized for synchronous and asynchronous clocks A design structure for a circuit for switching clock signals with logic devices using a glitchless clock multiplexer optimized for synchronous and asynchronous clocks. The design structure comprises a circuit having an asynchronous clock group and one or more synchr... | 12/27/2011 |
| 8026744 | Clock signal switching device, clock signal switching method, data bus switching device, and data bus switching method A clock signal switching device includes: a plurality of signal synchronization generation means for generating mask signals and synchronized switching signals; a plurality of clock signal mask means for generating masked clock signals; a synchronized switching sign... | 09/27/2011 |
| 8013637 | Clock signal selection circuit There is provided a clock signal selection circuit including: a first AND circuit (AND_A1) outputting a logical product signal of a clock selection signal and a first control signal; a second AND circuit (AND_A2) outputting a logical product signal of ... | 09/06/2011 |
| 8008949 | Clock selection for a communications processor having a sleep mode A clock selector operative on two clocks operating on different domains and responsive to a SELECT input provides a transition from a first clock to a second clock, and from a second clock to a first clock with a dead zone therebetween. The delay is provided by a do... | 08/30/2011 |
| 7961012 | Apparatus and method for preventing generation of glitch in a clock switching circuit An apparatus and for preventing a glitch in a clock switching circuit includes a select signal manager and a clock gate unit. The select signal manager generates a detect change signal, provides the detect change signal as an input signal for generating a clock gate... | 06/14/2011 |
| 7911240 | Clock switch-over circuits and methods Clock switch-over circuits and methods provide clock signals to clock routing networks. According to one embodiment, a multiplexer selects between a first clock signal and a second clock signal in response to a switch select signal received from a control circuit. A... | 03/22/2011 |
| 7911239 | Glitch-free clock signal multiplexer circuit and method of operation Techniques for the design and use of a digital signal processor, including for processing transmissions in a communications system. Reduced glitch occurs in switching from a first clock input to a second clock input driving a clock multiplexer. The clock multiplexer... | 03/22/2011 |
| 7911238 | Method of using a switch circuit in-phase switching clock signals A switch circuit for switching two clock signals includes a clock generator, a flip-flop and a multiplexer. The clock generator is to generate a reference signal whose cycle is the lowest common multiple of the cycles of the two clock signals. The flip-flop is to ge... | 03/22/2011 |
| 7884652 | Pulse signal generating device, transport device, image forming apparatus, and pulse generating method A pulse signal generating device includes: the plurality of encoders each of which outputs an encoder signal with a pulse period corresponding to the speed of an object to be detected; delay amount control unit that controls a relative delay amount with respect to a... | 02/08/2011 |
| 7816952 | Clock signal switching device, clock signal switching method, data bus switching device, and data bus switching method A clock signal switching device includes: a plurality of signal synchronization generation means for generating mask signals and synchronized switching signals; a plurality of clock signal mask means for generating masked clock signals; a synchronized switching sign... | 10/19/2010 |
| 7724044 | Digital multiplexor with multiple switching modes A digital signal multiplexor and multiplexing method are provided with which switching between different input signals is achieved without producing glitches in the output signal, even in the event of one or more of the input signals stopping and starting at unknown... | 05/25/2010 |
| 7679408 | Glitchless clock multiplexer optimized for synchronous and asynchronous clocks A circuit for switching clock signals with logic devices using a glitchless clock multiplexer optimized for synchronous and asynchronous clocks. The circuit comprises an asynchronous clock group and one or more synchronous clock group(s). The asynchronous group comp... | 03/16/2010 |
| 7671634 | Redundant clock switch circuit A redundant clock switch circuit that includes two delay circuits and control logic is presented. The first delay circuit is configured to delay a first clock signal to produce a first delayed clock signal, while the second delay circuit is configured to delay a sec... | 03/02/2010 |
| 7612587 | Semiconductor circuits Semiconductor circuit capable of selecting a corresponding adjusting parameter to adjust the received signal according to different voltages and frequencies. A voltage detector detects a voltage level of an external power voltage to generate a voltage detection sign... | 11/03/2009 |
| 7609095 | System and method for maintaining device operation during clock signal adjustments A system and method for seamlessly reprogramming clock frequencies includes a phase locked loop (PLL) that generates CPU and double data rate (DDR) clocks. A crystal is used to generate a reference clock. The CPU clock and the reference clock are inputs to a first m... | 10/27/2009 |
| 7605617 | Method for switching a system clock and clock synchronization unit A clock synchronization unit is provided for an electronic system, particularly for a microprocessor, that includes a first input for a first clock signal, a second input for a second clock signal, a third input for a select control signal, and an output for a syste... | 10/20/2009 |
| 7586337 | Circuit for switching between two clock signals independently of the frequency of the clock signals A clock switching circuit for switching between plural clock signals includes a selector for outputting a first control signal when a low speed clock is selected by a selection signal with a permission signal halted, and a second control signal when a high speed clo... | 09/08/2009 |
| 7586338 | Increasing the availability and redundancy of analog current outputs There is described a method for increasing an availability and a redundancy of an analog current output as well as an analog current output with increased availability and redundancy. To improve the availability and also the redundancy behavior of an analog current ... | 09/08/2009 |
| 7579879 | Voting scheme for analog signals A voting scheme for analog signals is described. An analog block is replicated to provide three analog blocks that are designed to have substantially the same analog output based on receiving substantially the same input. Voting is used to compare the analog outputs... | 08/25/2009 |
| 7554365 | Glitch-free clock switching circuit A glitch-free clock switching circuit receives a first clock signal and a second clock signal and outputs a third clock signal corresponding to the first clock signal or a fourth clock signal corresponding to the second clock signal according to a clock switching si... | 06/30/2009 |
| 7532043 | Signal detector output for cable driver applications The present disclosure relates to a system, apparatus and method for a line driver circuit to generate a signal detect (SD) signal when an invalid data signal is detected at its input. An invalid signal may be present either when no signal is available or when the l... | 05/12/2009 |
| 7471120 | Clock switch for generation of multi-frequency clock signal An improved clock switch in an integrated circuit chip that multiplexes two asynchronous clock signals to generate a multi-frequency clock signal in a manner that avoids glitches on the clock output line and meta-stable states within the switch. The clock switch doe... | 12/30/2008 |
| 7436238 | Integrated voltage switching circuit An integrated circuit can be switched between operating modes without the need for a dedicated mode selection pin. A circuit for operation at a specified maximum supply voltage comprises first and second supply terminals, a first signal input for application of a re... | 10/14/2008 |
| 7427881 | Clock loss detection and switchover circuit In one aspect, an embodiment provides a clock loss sense and switchover circuit and method in which clock switchover is responsive to loss of a primary signal and to additional switch command signaling. In another aspect, an embodiment provides a clock loss sense ci... | 09/23/2008 |
| 7423459 | Clock signal switching device, clock signal switching method, data bus switching device, and data bus switching method A clock signal switching device includes: a plurality of signal synchronization generation means for generating mask signals and synchronized switching signals; a plurality of clock signal mask means for generating masked clock signals; a synchronized switching sign... | 09/09/2008 |
| 7411429 | System and method for clock switching A system for clock-switching applied in the field of integrated circuits is described. A phase interpolator converts an input clock signal into a clock_A and a clock_B having a phase difference therebetween and transmitting the clock_A and the clock_B. A switch comm... | 08/12/2008 |
| 7375571 | Glitch free clock multiplexer that uses a delay element to detect a transition-free period in a clock signal A clock multiplexer circuit uses a delay element to detect a transition-free period in a first signal present on a D-input lead of an output latch. The output latch is then controlled to latch the stable value of the first signal, and to hold the value of the first ... | 05/20/2008 |
| 7358783 | Voltage, temperature, and process independent programmable phase shift for PLL A circuit provides a programmable phase shift feature, where the phase shift is programmably selectable by a user. This circuitry may be incorporated in a programmable logic device (PLD) or field programmable gate array (FPGA) to provide additional programmability f... | 04/15/2008 |
| 7352991 | Satellite signal distribution systems Various configurations and equipment are described for providing satellite television programming from multiple satellite antennas to receivers, particularly to receivers located in apartments within a multiple-dwelling unit and having one or more satellite televisi... | 04/01/2008 |
| 7340366 | Method and apparatus of temperature compensation for integrated circuit chip using on-chip sensor and computation means A method and apparatus of temperature compensation for an integrated circuit using on-chip circuits, sensors, and an algorithm. The chip includes an on-chip reference circuit, an on-chip sensor measuring a parameter relative to the reference, and an on-chip computat... | 03/04/2008 |
| 7339405 | Clock rate adjustment apparatus and method for adjusting clock rate A clock rate adjustment apparatus and a method for adjusting a clock rate of a clock for an optical storage system are provided. The clock rate adjustment apparatus comprises an indication provider, a throughput rate detector, and a clock generator. The method perfo... | 03/04/2008 |
| 7336116 | Clock supply circuit The clock supply circuit of the present invention comprises a plurality of clock supply paths and a clock gate circuit. The clock supply paths branch a clock signal and supply each of the branched clock signals to a plurality of sequential circuits via a buffer. The... | 02/26/2008 |
| 7334152 | Clock switching circuit A clock switching circuit comprises: a composite clock generation circuit, which is to receive a first clock, a second clock, and a clock switching execution signal for switching between the first clock and the second clock, and to make a level of the clock fixed to... | 02/19/2008 |
| 7333527 | EMI reduction using tunable delay lines The clock signal is the dominant source of electromagnetic interference (EMI) for many digital electronic devices. EMI generated by these electronic devices must be suppressed to avoid interference with other electronic devices and to satisfy FCC regulations. The pr... | 02/19/2008 |
| 7327173 | Delay-locked loop having a pre-shift phase detector A clock generator for generating an output clock signal synchronized with an input clock signal having first and second adjustable delay lines. The first adjustable delay lines is adjusted following initialization of the clock generator to expedite obtaining a lock ... | 02/05/2008 |
| 7321244 | Clock switching device and clock switching method A clock switching device capable of automatic switching to a clock distribution system for back-up without interrupting processing of the device, which includes an abnormality detection unit which detects lack of coincidence in a logical level between a current cloc... | 01/22/2008 |
| 7321254 | On-chip automatic process variation, supply voltage variation, and temperature deviation (PVT) compensation method An on-chip substrate voltage controller which includes a plurality of chains of interconnected loaded ring oscillators connected to a multiplexer, where the multiplexer is configured to average the outputs from all the chains of interconnected loaded ring oscillator... | 01/22/2008 |
| 7319345 | Wide-range multi-phase clock generator A wide-range multi-phase clock generator having a first clock generating circuit, a frequency divider circuit, and a plurality of multiplexers. The first clock generating circuit generates a plurality of first clock signals, each having a first frequency and a respe... | 01/15/2008 |
| 7319728 | Delay locked loop with frequency control A delay locked loop includes a delay line for delaying an input signal generated from an external signal. A delay controller controls the delay line to keep the external and internal signals synchronized. The delay locked loop also includes cycle control circuitry f... | 01/15/2008 |
| 7315189 | Retiming circuits for phase-locked loops Circuits and methods for retiming a frequency-divided clock are provided. A first sampling circuit samples the frequency-divided clock with a rising edge of a sampling clock. A second sampling circuit samples the frequency-divided clock with a falling edge of the sa... | 01/01/2008 |
