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| Number | Title | Issue Date |
| 8054105 | Sample hold circuit and method for sampling and holding signal A sample hold circuit and a method for sampling and holding a signal are provided. The sample hold circuit includes a sample unit, a direct current (DC) voltage elimination unit, and a hold unit. When the sample hold circuit is in a first state, the sample unit samp... | 11/08/2011 |
| 7973570 | Sample-and-hold (S/H) circuit A sample-and-hold circuit (100) is provided that that includes a sample-and-hold switch (125), an integrator circuit (180) designed to generate an output voltage (VOUT) signal, and a bias voltage (VBIAS) source (185)... | 07/05/2011 |
| 7683677 | Sample-and-hold amplification circuits A sample-and-hold amplification circuit comprises an amplifier, a first sample-and-hold unit, and a second sample-and-hold unit. The amplifier has an input terminal and an output terminal. The first sample-and-hold unit is coupled to the input terminal and the outpu... | 03/23/2010 |
| 7403046 | Sample-and-hold circuits A sample-and-hold circuit including a first switch, a first capacitor and an amplifier is provided. The switch has a first terminal to receive the input signal and transmit it to a second terminal thereof in the sample period. The first terminal of the first capacit... | 07/22/2008 |
| 7397287 | Sample hold circuit and multiplying D/A converter having the same A sample hold circuit includes an op-amp, first capacitors provided on an inverting side of the op-amp and second capacitors provided on a non-inverting side. The sample hold circuit is configured such that a total capacitance of the first and second capacitors to w... | 07/08/2008 |
| 7385427 | Sample-and-hold circuits having reduced channel conductance variation and methods of operation thereof An electronic device, such as a sample-and-hold circuit, includes a field effect transistor (FET), a capacitor, and a voltage offset circuit. The FET is configured to receive a signal at a first terminal thereof and selectively provide the signal to a second termina... | 06/10/2008 |
| 7336749 | Statistical margin test methods and circuits Margin-testing circuits and methods rely upon the statistics of sampled data to explore the margin characteristics of received data. One margining circuit samples an incoming data stream N times at each of many sample points, each sample point representing a unique ... | 02/26/2008 |
| 7315200 | Gain control for delta sigma analog-to-digital converter Gain control for delta sigma analog-to-digital converter. A method is disclosed for driving the input of an integrator in a delta-sigma converter having an amplifier with a non-inverting input, an output and a positive input connected to a reference voltage and an i... | 01/01/2008 |
| 7304518 | Track and hold circuit A track and hold circuit (1) comprising:—a linear amplifier (2) receiving a differential analog signal (D+, D−) and being controlled by a first binary clock signal (H+) having a first phase,—the linear amplifier (2) providing a feed-forwar... | 12/04/2007 |
| 7302055 | Discharging envelope detector A receiver to detect pulses on a home phone wiring network using envelope detection. The receiver comprises an integrating capacitor charged by a first current source responsive to a differential signal propagated on the wiring network, and discharged by a FET in co... | 11/27/2007 |
| 7295042 | Buffer A switched capacitor buffer operating by the push-pull method is taught. The buffer may include a pull-up device and a pull-down device. A switched capacitor circuit may be used to control the pull-up device and the pull-down device to achieve accurate push-pull ope... | 11/13/2007 |
| 7282991 | On-chip amplifier/line driver compensation circuit An embodiment of the present invention includes an amplifier on an integrated circuit, with the amplifier having positive and negative inputs, and positive and negative outputs. A first feedback capacitor is on the integrated circuit between the positive input and t... | 10/16/2007 |
| 7279940 | Switched-capacitor circuit with time-shifted switching scheme A switched-capacitor circuit for sampling a pair of differential input signals includes a first bootstrapped switch and a first non-boosted switch connected in parallel between a first output terminal of an amplifier and a first feedback node of the switched-capacit... | 10/09/2007 |
| 7271625 | Sample-and-hold device having input stages of amplifier coupled to capacitors A sample-and-hold device including first and second capacitors, first and second switches, amplifier and feedback network is provided. The amplifier includes first and second input stages, output stage and switchable bias current source. The first switch and the fir... | 09/18/2007 |
| 7252085 | Device for inhalation therapy The invention relates to a device for inhalation therapy. Said device comprises an aerosol-producing device for spraying a liquid (3), preferably comprising a membrane (1), a support unit (6), an electromechanical transducer unit (7), and... | 08/07/2007 |
| 7250795 | High-speed, low-power input buffer for integrated circuit devices A high-speed, low-power input buffer for an integrated circuit device in which the input voltage (VIN) is coupled to both a pull-up and a pull-down transistor. In accordance with a specific embodiment, the input buffer utilizes a reference voltage input (VREF) durin... | 07/31/2007 |
| 7239183 | Active current mode sampling circuit The invention relates to an active current mode sampling circuit comprising an operational amplifier (103) and at least one switched capacitor (C2, C2a, C2b). In order to reduce the power consumption of such a circuit... | 07/03/2007 |
| 7236017 | High speed sample-and-hold circuit The use of a dynamic current bias technique to dynamically bias a voltage switch of a sample-and-hold circuit is disclosed. Dynamically biasing the voltage switch mitigates nonlinear distortion caused by VBE (VGS) variation during charging and ... | 06/26/2007 |
| 7218154 | Track and hold circuit with operating point sensitive current mode based offset compensation A track and hold (or sample and hold) offset compensated amplifier circuit that performs offset compensation in response to a comparison of sign (or sign and value) of the current forced to the output terminal of operational amplifier in order to keep it at the pote... | 05/15/2007 |
| 7199663 | Use of analog-valued floating-gate transistors for parallel and serial signal processing Analog-valued floating-gate transistors are used as trimmable circuit components for modifying and/or controlling the gain, phase, offset, frequency response, current consumption, and/or transfer function of signal pathways in parallel and/or serial processing circu... | 04/03/2007 |
| 7196577 | Amplifier with capacitor selection A selectable-gain amplifier selectively couples different capacitors and feedback networks to a gain stage to provide operating characteristics that may include constant bandwidth operation. An interpolated VGA includes pairs of gm cells with cross-connected outputs... | 03/27/2007 |
| 7187237 | Use of analog-valued floating-gate transistors for parallel and serial signal processing Analog-valued floating-gate transistors are used as trimmable circuit components for modifying and/or controlling the gain, phase, offset, frequency response, current consumption, and/or transfer function of signal pathways in parallel and/or serial processing circu... | 03/06/2007 |
| 7187215 | High dynamic range current-mode track-and-hold circuit Embodiments of the current-mode track and hold circuit comprise a cascode input stage, a dynamic biasing stage, a cascode output stage, and a switch operable to interconnect the input stage and the output stage. The input stage is connected to receive an input curre... | 03/06/2007 |
| 7173465 | High-speed, current-driven latch A high-speed, current-driven latch is provided. The latch conducts a current and includes an output, a SET circuit and a RESET circuit. The output is variable between a first state and a second state. The SET circuit conducts the current present in the latch at the ... | 02/06/2007 |
| 7136000 | Selective offset adjustment of a track and hold circuit A track/hold circuit with an offset adjustment that can be used to compensate for offset errors from other parts of the system containing the track/hold circuit. The offset adjustment may be provided by impressing a voltage at an electrode of a capacitor of the trac... | 11/14/2006 |
| 7132862 | Analog buffer and method for driving the same In an analog buffer and a method for driving the same, by providing a pair of switches at a last comparing unit, a voltage level of an output signal is precharged as high as a source voltage level during a first offset period in an Nth initializing period, the volta... | 11/07/2006 |
| 7113116 | Sample and hold apparatus An acquisition and averaging circuit is provided in which, during a sampling phase capacitors in sample blocks 4 and 6 are sequentially connected to the input signal to sample it and are then isolated so as to hold the sample. The capacitors are then c... | 09/26/2006 |
| 7113031 | Audio amplifier circuit with suppression of unwanted noise when powered on from standby A power amplifier circuit comprising at least one first amplifier having a first input receiving an input voltage through at least one first coupling capacitor and connected to an output of the first amplifier, and having a second input, separate from the first inpu... | 09/26/2006 |
| 7109761 | Comparator circuit A reference voltage and an input signal voltage are applied to gates of FETs each equipped with a LOCOS-drain structure, respectively, and currents according to the voltages are made to flow from a power supply voltage Vbat to drain sides through resistors and sourc... | 09/19/2006 |
| 7068202 | Architecture for an algorithmic analog-to-digital converter An algorithmic analog-to-digital converter (ADC) includes a sample-and-hold circuit and an ADC processing unit operating in parallel and sharing a single operational amplifier. The ADC processing unit includes an MDAC with a switched capacitor topology and a sub-ADC... | 06/27/2006 |
| 7061324 | Use of analog-valued floating-gate transistors for parallel and serial signal processing Analog-valued floating-gate transistors are used as trimmable circuit components for modifying and/or controlling the gain, phase, offset, frequency response, current consumption, and/or transfer function of signal pathways in parallel and/or serial processing circu... | 06/13/2006 |
| 7061291 | Linear voltage tracking amplifier for negative supply slew rate control Circuitry is provided for controlling the slew rate of a negative output supply. The slew rate control circuitry includes an NMOS FET, a feedback resistor connected across the drain and the gate of the NMOS FET, an input resistor connected to the gate of the NMOS FE... | 06/13/2006 |
| 7058528 | Automated optimization of asymmetric waveform generator LC tuning electronics Disclosed is method of controlling an asymmetric waveform generator including the steps of providing a reference timer signal, and generating an asymmetric waveform as a combination of a first sinusoidal wave having a first frequency and a second sinusoidal wave hav... | 06/06/2006 |
| 7052180 | LED junction temperature tester An instrument measures the LED junction temperature directly by taking advantage of the linear relationship between the forward current driven through the LED, the forward drop of the LED, and the junction temperature to determine the LED junction temperature. | 05/30/2006 |
| 7049855 | Area efficient waveform evaluation and DC offset cancellation circuits Analog circuits for providing one or more waveform parameters, e.g., the DC offset or average, of an analog input signal. Separate biasing is not necessarily required. Some embodiments comprise field-effect-transistors (FETs) configured in various diode-connected co... | 05/23/2006 |
| 7049860 | Method and circuit for controlling a resistance of a field effect transistor configured to conduct a signal with a varying voltage The present invention relates to a replica network for linearizing switched capacitor circuits. A bridge circuit with a MOSFET resistor disposed in a resistor branch of the bridge circuit is provided. A noninverting terminal of an operational amplifier is connected ... | 05/23/2006 |
| 7038544 | Use of analog-valued floating-gate transistors for parallel and serial signal processing Analog-valued floating-gate transistors are used as trimmable circuit components for modifying and/or controlling the gain, phase, offset, frequency response, current consumption, and/or transfer function of signal pathways in parallel and/or serial processing circu... | 05/02/2006 |
| 7002506 | Providing pipe line ADC with acceptable bit error and power efficiency combination A pipeline ADC implemented with both general charge redistribution stages and flip-around charge redistribution stages. Using the flip-around charge redistribution stages leads to reduced power/area consumption, but could lead to accumulation and propagation of erro... | 02/21/2006 |
| 6992509 | Switched-capacitor sample/hold having reduced amplifier slew-rate and settling time requirements A switched-capacitor sample/hold circuit and method having reduced slew-rate and settling time requirements provides for lower-cost and/or lower-power implementation of sample/hold circuits and/or reduced error due to amplifier characteristics. The switched-capacito... | 01/31/2006 |
| 6747489 | Frequency multiplying circuitry with a duty ratio varying little Frequency multiplying circuitry includes a couple of integrator circuits. The one integrator circuit charges a capacitor with a larger time constant via a resistor when an input clock signal is in its high level and then discharges it with a smaller time constant wh... | 06/08/2004 |
