Quotables
"I watched his countenance closely, to see if he was not deranged ... and I was assured by other senators after he left the room that they had no confidence in it."
U.S. Senator Smith of Indiana ; After seeing Samuel Morse demonstrate the telegraph.
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| Number | Title | Issue Date |
| 7391254 | Circuit and method of generating internal supply voltage in semiconductor memory device An internal supply voltage generation circuit includes first and second driving circuits and a resistive device. The first driving circuit receives a feedback voltage from a first node and generates a first output voltage based on first and second reference voltages... | 06/24/2008 |
| 7382167 | Circuit and method for controlling hysteresis for bilevel signal transitions An output signal is controlled with adjustable hysteresis in response to a variable voltage input signal. One or more signals derived from the input signal are respectively compared with first and second reference voltages of different magnitudes. The output signal ... | 06/03/2008 |
| 7366244 | Method and system for antenna interference cancellation A wireless communication system can comprise two or more antennas that interfere with one another via free space coupling, surface wave crosstalk, dielectric leakage, or other interference effect. The interference effect can produce an interference signal on one of ... | 04/29/2008 |
| 7352824 | Multilevel pulse position modulation for efficient fiber optic communication Decreasing the average transmitted power in an optical fiber communication channel using multilevel amplitude modulation in conjunction with Pulse Position Modulation (PPM). This multilevel PPM method does not entail any tradeoff between decreased power per channel ... | 04/01/2008 |
| 7324038 | Subranging analog to digital converter with multi-phase clock timing An N-bit analog to digital converter includes a reference ladder, a track-and-hold amplifier connected to an input voltage, a coarse ADC amplifier connected to a coarse capacitor at its input and having a coarse ADC reset switch controlled by a first clock phase of ... | 01/29/2008 |
| 7295044 | Receiver circuits for generating digital clock signals A digital clock generation circuit (and a method for operating the same). The digital clock generation circuit includes a first, a second, a third differential comparator circuits. The first differential comparator circuit receives the positive differential clock si... | 11/13/2007 |
| 7276901 | Method for shunt detection in sensors For monitoring a sensor using differential voltage evaluation for detecting a short circuit to ground and/or to supply voltage UB, a first resistor and a second resistor R1, R2 are assigned to the sensor, a sum voltage is determined ... | 10/02/2007 |
| 7271755 | Resistor ladder interpolation for PGA and DAC A voltage interpolation circuit includes a resistive ladder connected between ground and a voltage input and having a plurality of resistors with voltage taps between the resistors. An amplifier (optionally) has first and second capacitors connected together at thei... | 09/18/2007 |
| 7215721 | Method and system for decoding multilevel signals A multilevel optical receiver can comprise a plurality of comparators that generally correspond with the number of levels in a multilevel data stream. Each comparator can be individually controlled and fed a decision threshold in order to decode a multilevel signal.... | 05/08/2007 |
| 7215268 | Signal converters with multiple gate devices An analog to digital converter including a plurality of multiple independent gate field effect transistors (MIGFET) that provide a plurality of digital output signals, is provided. Each MIGFET of the plurality of MIGFETs may have first gate for receiving an analog s... | 05/08/2007 |
| 7212580 | Multi-level signal clock recovery technique Clock recovery of a multi-level (ML) signal can be performed in a two-step process. First, the transitions within the ML signal can be detected by a novel transition detector (TD). And second, the output of the TD circuit can comprise a pseudo-non-return-to-zero (pN... | 05/01/2007 |
| 7190212 | Power-up and BGREF circuitry Circuitry including a BGREF (bandgap voltage reference) comparator including a plurality of MOS transistors that compare a resistor divided supply voltage to a function of at least two process parameter voltages. ... | 03/13/2007 |
| 7173551 | Increasing data throughput in optical fiber transmission systems Data throughput rates are increased in an optical fiber communication system without requiring replacement of the existing optical fiber in a link. Channel throughput is increased by upgrading the components and circuitry in the head and terminal of an optical fiber... | 02/06/2007 |
| 7149256 | Multilevel pulse position modulation for efficient fiber optic communication Decreasing the average transmitted power in an optical fiber communication channel using multilevel amplitude modulation in conjunction with Pulse Position Modulation (PPM). This multilevel PPM method does not entail any tradeoff between decreased power per channel ... | 12/12/2006 |
| 7126408 | Method and apparatus for receiving high-speed signals with low latency An apparatus and method for receiving high-speed signals having a wide common-mode range with low input-to-output latency. In one embodiment, the receiver includes an integrator to accumulate charge in accordance with an input signal during an integration time inter... | 10/24/2006 |
| 7126509 | Micropower logarithmic analog to digital conversion system and method with offset and temperature compensation A logarithmic analog-to-digital converter system is disclosed. The system includes a transconductor for receiving an input signal and for producing a transconductor output signal at a transconductor output, a logarithmic circuit unit that is coupled to an input of t... | 10/24/2006 |
| 7123676 | Method and system for antenna interference cancellation A wireless communication system can comprise two or more antennas that interfere with one another via free space coupling, surface wave crosstalk, dielectric leakage, or other interference effect. The interference effect can produce an interference signal on one of ... | 10/17/2006 |
| 7109764 | PLL clock signal generation circuit A PLL clock signal generation circuit comprising a phase comparator, a charge pump circuit, a filter circuit, a voltage control oscillator and a divider, wherein a multiple rate control circuit is further included which detects a state of the reference voltage (outp... | 09/19/2006 |
| 7049876 | Level shift circuits and related methods A level shifting circuit functions by taking an input signal, producing a complement of the input signal, applying the input signal and its complement to comparable voltage divider pairs to set up a differential input signal that is applied to a comparator that prod... | 05/23/2006 |
| 7034580 | Capacitor charging methods and apparatuses that use a secure parallel monitoring circuit A capacitor charging circuit and method including a plurality of serially connected capacitors and parallel monitor circuits connected in parallel on a one-to-one basis to the capacitors. Each one of parallel monitor circuits applies a direct-current source voltage ... | 04/25/2006 |
| 6999019 | Subranging analog-to-digital converter with integrating sample-and-hold A subranging analog-to-digital converter (ADC) includes an integrating sample-and-hold circuit. The integrating sample-and-hold circuit is configured to sample an input voltage by charging at least one capacitor by coupling a current proportional to the input voltag... | 02/14/2006 |
| 6977532 | Dual differential comparator circuit with full range of input swing The differential comparator circuit for receiving an input voltage within a pre-determined range, amplifying the input voltage, and outputting an output voltage is provided. The circuit includes: a first differential comparator for receiving the input voltage within... | 12/20/2005 |
| 6965262 | Method and apparatus for receiving high speed signals with low latency An apparatus and method for receiving high-speed signals having a wide common-mode range with low input-to-output latency. In one embodiment, the receiver includes an integrator to accumulate charge in accordance with an input signal during an integration time inter... | 11/15/2005 |
| 6956411 | Constant Rswitch circuit with low distortion and reduction of pedestal errors A low distortion, high frequency switch circuit for selectively coupling an input voltage terminal to an output voltage terminal includes a switching device coupled to the input voltage terminal and the output voltage terminal, a charge storage device, and a first, ... | 10/18/2005 |
| 6954423 | Analog implementation of linear transforms Analog phase-shift elements connect each of a plurality of input nodes to each of a plurality of output nodes, wherein each component is adapted to produce a phase shift in a periodic signal processed therethrough. A linear transformation of a data set of discrete v... | 10/11/2005 |
| 6750796 | Low noise correlated double sampling modulation system A charge balancing modulation system for digitizing the output of a variable impedance sensor utilizes synchronous excitation of the input sensor and AC coupling of the analog input signal. The modulation system also implements correlated double sampling to provide ... | 06/15/2004 |
| 6714052 | Method and apparatus for passive component minimization of connector pins in a computer system In a computer system, a passive component minimization of connector pins configuration includes a motherboard and daughterboard. The daughterboard includes a selection switch coupled via passive components to a single connector pin, according to a prescribed state o... | 03/30/2004 |
| 6693465 | Open input sense for differential receiver Circuitry is disclosed for detection of open inputs on an enhanced differential receiver. A pulldown terminator is coupled to the inputs of the enhanced differential receiver. If the differential inputs are not actively driven, the voltage on both differe... | 02/17/2004 |
| 6677785 | Power level detection circuit A power level detection circuit detects the voltage level of a power source. The power level detection circuit has a first voltage level detector having an input coupled to the power source and outputting a first signal representative of an upper boundary... | 01/13/2004 |
| 6535028 | Data bus fault detection circuit and method A receiver circuit is connected to a differential serial bus having first and second signal conductors. The receiver circuit includes a fault detection circuit which generates a difference signal representing a difference between a first signal on the fir... | 03/18/2003 |
| 6281831 | Analog to digital converter An A/D converter having a plurality of thresholding circuits corresponding to bits of output digital data, each of which includes odd number of inverters serially connected from a first stage to a last stage. The first stage inverter of the thresholding c... | 08/28/2001 |
| 6278724 | Receiver in a spread spectrum communication system having low power analog multipliers and adders A signal reception apparatus in the spread spectrum communication system requires only a small amount of circuitry and consumes a small amount of electric power. A quadrature detector decomposes received signals into in-phase components and quadrature com... | 08/21/2001 |
| 6271690 | Discriminator A discriminator capable of generating a multi-level signal with less restrictions is provided. In a discriminator D1, a wave-shaping circuit 3 shapes the waveform of one branched multi-level signal MS, according to a control signal CS from a control signa... | 08/07/2001 |
| 6208175 | Circuit arrangement for the evaluating a binary signal defined by current threshold values A circuit arrangement for evaluating a binary signal defined by two current thresholds, particularly the output signal of an active sensor [(1')], comprises a current source [(IQ'_,IQ11,IQ12,IQ13)] that can consist of indi... | 03/27/2001 |
| 6157221 | Three input comparator A three input comparator facilitates the comparison of a signal to the greater of two different reference voltages in a manner which mitigates propagation delay. A first differential pair of transistors facilitates comparison of the two reference voltages... | 12/05/2000 |
| 6154065 | Sense amplifier circuit A sense-amplifier circuit comprising a plurality of sub-sense-amplifiers corresponding to respective reference potentials can operate fast when used for a multivalued information memory. The sense amplifier circuit is composed of sub-sense-amplifiers havi... | 11/28/2000 |
| 6137306 | Input buffer having adjustment function for suppressing skew An input buffer of the present invention includes: a plurality of receiver circuits for performing different phase adjustments on an input signal, and outputting the differently phase-adjusted signals; a pattern detection circuit for detecting a period of... | 10/24/2000 |
| 6078627 | Circuit and method for multilevel signal decoding, descrambling, and error detection At least two level detectors compare a multilevel signal to respective prescribed voltage levels to produce corresponding streams of bits. These bit streams are repeatedly delayed in respective digital delay lines, and bits from the digital delay lines ar... | 06/20/2000 |
| 6028456 | Dual-threshold comparator circuit utilizing a single input pin A dual-threshold voltage comparator circuit utilizes a single input pin of an integrated circuit and an external resistor network. Appropriate selection of the resistors comprising the resistor network permits independent setting of the dual thresholds of... | 02/22/2000 |
| 5949280 | Multivalued FSK demodulation window comparator A multivalued FSK demodulation window comparator includes an MSB comparator, an LSB comparator, a reception electric field strength detector, and a reference voltage generating circuit. The MSB comparator determines at least the polarity of a frequency sh... | 09/07/1999 |
