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| Number | Title | Issue Date |
| 7893726 | Leakage compensation and improved setup/hold time in a dynamic flip-flop A dynamic flip-flop includes first and second input stages forming a differential input stage adapted to receive differential data. The flip-flop is reset in response to a reset signal. To ensure proper operation, a transistor disposed between the first and second i... | 02/22/2011 |
| 7821303 | Comparator and A/D converter A comparator used in a parallel-type A/D converter, wherein a comparator 100 includes reset transistors mra and mrb. When the comparator 100 is in the Reset state, the inverted signal /CLK of the clock signal is given to the PMOS reset transistors mra ... | 10/26/2010 |
| 7800411 | System and method for providing a strobed comparator with reduced offset and reduced charge kickback A system and method is disclosed for providing a strobed comparator with reduced offset and reduced charge kickback. The strobed comparator circuit comprises a differential pair of transistors coupled to a first switch circuit, a regenerative latch circuit, a first ... | 09/21/2010 |
| 7777529 | Leakage compensation in dynamic flip-flop A dynamic flip-flop includes a leakage compensation circuit enabling operation over a wide range of frequencies. Nodes of the dynamic flip-flop store the flip-flop's state. The leakage compensation circuit drains leakage currents from these nodes to prevent the node... | 08/17/2010 |
| 7701258 | Latch A latch includes: an amplifying circuit, for receiving a first bias current in a first state for amplifying an input signal to generate an amplified signal; a latching unit, for latching the amplified signal and receiving a second bias current in a second state to o... | 04/20/2010 |
| 7692452 | Semiconductor chip and power gating method thereof A semiconductor chip may include an internal circuit, at least one power gating transistor, a system manager, and/or at least one current regulator. The at least one power gating transistor may be configured to switch a supply of at least one drive voltage into the ... | 04/06/2010 |
| 7679406 | Comparator having a preamplifier with power saved while latching data In a comparator, a differential amplifier has a pair of transistors receiving a signal to be compared for differential amplification, and a current mirror load circuit for outputting a differential output signal in accordance with the relationship in magnitude of th... | 03/16/2010 |
| 7545180 | Sense amplifier providing low capacitance with reduced resolution time A sense amplifier circuit provides for high speed sensing with a high speed read operation, with a low capacitance and a low resolution time. The sense amplifier circuit includes a latch circuit having a first inverter circuit and a second inverter circuit cross cou... | 06/09/2009 |
| 7449922 | Sensing circuitry and method of detecting a change in voltage on at least one input line Sensing circuitry and a method of operating such sensing circuitry are provided. The sensing circuitry has voltage change detection circuitry for detecting a change in voltage on at least one input line and for producing at least one output signal indicative of that... | 11/11/2008 |
| 7446573 | Comparator systems and methods In accordance with an embodiment of the present invention, a comparator system includes a plurality of multiplexers adapted to multiplex a number of differential input signals and a number of differential reference signals. A differencing circuit receives a differen... | 11/04/2008 |
| 7443207 | Differential output circuit with stable duty A differential output circuit includes a bias circuit connected with a first voltage. An input circuit section includes first and second MOS transistors of a first conductive type, and the first and second MOS transistors are connected with the first voltage through... | 10/28/2008 |
| 7417481 | Controlling signal states and leakage current during a sleep mode A circuit includes an input terminal, an output terminal and a latch. The input terminal receives an input signal. The latch is programmable with a value. The latch communicates the input signal to the output terminal in response to the circuit not being in a sleep ... | 08/26/2008 |
| 7414434 | Input circuit An input circuit is provided that can identify three states of an external signal without complicated voltage adjustment and that can reduce the power consumption in a standby state. The input circuit includes: four resistor elements serially provided between differ... | 08/19/2008 |
| 7414908 | Magnetic memory device A Magnetic Random Access Memory (MRAM), in which very little current flows through MTJ elements and very little voltage is applied across them, the MRAM being provided with sense-amplifiers capable of amplifying the potential difference between their corresponding p... | 08/19/2008 |
| 7400177 | Amplifier circuit having constant output swing range and stable delay time Provided is an amplifier circuit having a constant output swing range and a stable delay time, where the amplifier circuit includes a first bias unit, a second bias unit, a comparison unit, and an amplifier unit, and the first bias unit responds to an internal refer... | 07/15/2008 |
| 7397286 | Flip-flop circuit including latch circuits A flip-flop circuit capable of inhibiting current consumption as well as the circuit scale from increase is provided. This flip-flop circuit comprises a first latch circuit including first and second inverter circuits. A first power supply line capable of switching ... | 07/08/2008 |
| 7394678 | Over-driven access method and device for ferroelectric memory An over-driven access method and device for ferroelectric memory. When accessing the data stored in a ferroelectric memory, the invention further provides an over-driven current to slightly reduce/raise the voltages in bit lines BL and BL′ to further enlarge the v... | 07/01/2008 |
| 7372307 | Efficient current monitoring for DC-DC converters A current monitoring circuit for DC-DC switching converters includes a track and latch comparator circuit (30) having a preamplifier (32) that is controlled independently of a latch circuit (34). The comparator is small and operates very fast an... | 05/13/2008 |
| 7368955 | Current-balanced logic circuit In accordance with some embodiments, a current-balanced logic circuit includes a first sense amplifier, a second sense amplifier, and a current-source transistor which provides bias current to the first and second sense amplifiers. The first and second sense amplifi... | 05/06/2008 |
| 7362153 | Receiver latch circuit and method In some embodiments, a receiver latch circuit, includes a dynamic latch having at least one input terminal to receive an input data signal and at least one latch terminal. The dynamic latch is adapted to generate an amplified output data signal based at least in par... | 04/22/2008 |
| 7355914 | Methods and apparatuses for a sense amplifier Various apparatuses and methods in which a sense amplifier circuit couples to a current source to provide current for the sense amplifier circuit and also couples to one or more memory cells to sense a charge being stored by each memory cell. Store protection circui... | 04/08/2008 |
| 7352215 | High speed latch comparators In a latch circuit having a bistable pair of cross connected transistors of a first polarity and a third transistor of a second polarity, a current signal greater than a bias current is received at a latch circuit port, amplified with the third transistor, and appli... | 04/01/2008 |
| 7349241 | SRAM circuitry A static ram cell is described. The cell includes a pair of cross-coupled transistors and a pair of diode-connected transistors operated from a wordline that provides power to the cell. The cell has three main operating modes, reading, writing, and data retention. R... | 03/25/2008 |
| 7330050 | Storage elements for a configurable IC and method and apparatus for accessing data stored in the storage elements Some embodiments provide a circuit for accessing stored data in a configurable IC that includes several configurable circuits. The IC also includes several storage circuits. Each storage circuit has (1) several storage elements for storing data for the configurable ... | 02/12/2008 |
| 7330387 | Integrated semiconductor memory device An integrated semiconductor memory device includes a sense amplifier that is connected to a first bit line via a first output connection and is connected to a second bit line via a second output connection. A memory cell to store a first or a second memory state is ... | 02/12/2008 |
| 7323911 | Differential sense amplifier circuit and method triggered by a clock signal through a switch circuit A differential sense amplifier is described that can be configured as a preamplifier or a latch circuit as triggered by a clock signal connected to a switch circuit. When the clock signal is set at a first signal level, the switch circuit in the differential sense a... | 01/29/2008 |
| 7313040 | Dynamic sense amplifier for SRAM A dynamic sense amplifier for static random access memory (SRAM) is provided. The dynamic sense amplifier includes a pre-amplifier configured to amplify small input signals according to a first clock signal, and a main sense-latch coupled to the pre-amplifier, where... | 12/25/2007 |
| 7307867 | Over-driven access method and device for ferroelectric memory An over-driven access method and device for ferroelectric memory. When accessing the data stored in a ferroelectric memory, the invention further provides an over-driven current to slightly reduce/raise the voltages in bit lines BL and BL′ to further enlarge the v... | 12/11/2007 |
| 7304903 | Sense amplifier circuit A sense amplifier circuit includes a first double-gate metal oxide semiconductor field effect transistor (DGMOSFET) having a first gate defining a first input to the circuit, a second gate and an output being coupled to a first output of the circuit and a second DGM... | 12/04/2007 |
| 7301373 | Asymmetric precharged flip flop A flip-flop circuit includes a differential stage coupled to a latch stage. The differential stage comprises cross-coupled dynamic logic and only provides a single output to the latch stage. During an evaluation phase, the state of a data input signal is sensed. Dep... | 11/27/2007 |
| 7298180 | Latch type sense amplifier A latch type sense amplifier includes a latch unit, an amplifying unit and a circuit module for charging or discharging the latch unit. The latch unit is configured by two sets of serially coupled PMOS and NMOS transistors, whose gates and drains are cross-coupled. ... | 11/20/2007 |
| 7295043 | Differential output circuit for improving bandwidth A differential output circuit includes first and second inputs, first and second outputs, a resistor element connected between the outputs, first and second N-channel MISFETs, and first and second P-channel MISFETs. The inputs respectively receive first and second c... | 11/13/2007 |
| 7279939 | Circuit for differential current sensing with reduced static power Returning to FIG. 2, sense circuit 201 represents the circuit that must sense the signaling on an interconnect. NMOS device 202 is always on so that there is a continuous path to ground whenever PMOS driver 204 is on. Since leakage power ... | 10/09/2007 |
| 7269754 | Method and apparatus for flexible and programmable clock crossing control with dynamic compensation A system and method for crossing clocks from a source clock to a destination clock is disclosed. In one embodiment, a source clock phase enable signal is used to enable a set of latch components to selectively input a source clock pulse. The outputs of the latch com... | 09/11/2007 |
| 7262639 | High-speed comparator A differential comparator with improved bit-error rate performance operating with a low supply voltage. The differential comparator includes a first pair of transistors receiving a differential input. A second pair of transistors is coupled to the first pair of tran... | 08/28/2007 |
| 7263016 | Method and system for pre-charging and biasing a latch-type sense amplifier A method and system for pre-charging and biasing a latch-type sense amplifier are described. According to an embodiment of the invention, the data latch portion of the latch-type sense amplifier includes two cross-coupled inverters having two output nodes, and two i... | 08/28/2007 |
| 7251148 | Matchline sense circuit and method A matchline sense circuit for detecting a rising voltage on a matchline of a CAM array is disclosed. The circuit initially precharges a matchline to ground before turning on a current source to supply current to the matchline and raise the voltage of the matchline. ... | 07/31/2007 |
| 7242629 | High speed latch circuits using gated diodes A sense amplifier circuit comprises (1) an isolation device comprising a control terminal and first and second terminals, the first terminal of the isolation device coupled to a signal line, (2) a gated diode comprising first and second terminals, the first terminal... | 07/10/2007 |
| 7233173 | System and method for providing a low jitter data receiver for serial links with a regulated single ended phase interpolator A system and method is disclosed for providing a clock and data recovery circuit that comprises a low jitter data receiver. The low jitter data receiver comprises a phase interpolator, an amplifier unit and a data sampling comparator. The phase interpolator and the ... | 06/19/2007 |
| 7233172 | Differential amplifier circuit capable of accurately amplifying even high-speeded signal of small amplitude A differential amplifier circuit has a latch unit and a differential input portion. A minute current is kept to flow through the differential input portion. Therefore, the differential amplifier circuit can accurately amplify even a signal high in speed and small in... | 06/19/2007 |
