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| Number | Title | Issue Date |
| 8130031 | Tunable metamaterial Examples of the present invention include a metamaterial comprising a plurality of resonators disposed on a substrate, the substrate comprising a dielectric support layer and a relatively thin semiconductor layer, having a Schottky junction between at least one cond... | 03/06/2012 |
| 8072260 | Configurable clock network for programmable logic device In a programmable logic device having high-speed serial interface channels, a clock distribution network for providing one or more high-speed clocks to dynamic phase alignment circuitry of those high-speed serial interfaces includes at least one bus that is segmenta... | 12/06/2011 |
| 7920021 | Method of applying wire voltage to semiconductor device A method of applying a wire voltage to a semiconductor device including a plurality of active regions and a field region insulating the plurality of active regions, wherein the field region includes a plurality of wires. The method includes applying an operating vol... | 04/05/2011 |
| 7893757 | Multi-chip package semiconductor device An efficient logic chip operating power supply having digital circuits in a multi-chip package is provided. A multi-chip package semiconductor device fabricated in common with a driver chip having analog circuits and a logic chip having digital circuits, a logic chi... | 02/22/2011 |
| 7872521 | CCD device and method of driving same Disclosed is a CCD device in which a charge transfer register of a CCD structure is connected to a charge detector via an output gate and has a reset gate between the charge detector and a reset drain, and an output gate pulse opposite in phase from a reset pulse ap... | 01/18/2011 |
| 7859328 | Substrate stress measuring technique A system, including: a first current mirror having a first current, formed of multiple devices disposed on a substrate, where, when a stress is present, a behavior of a device of the multiple devices forming the first current mirror depends on a direction in which t... | 12/28/2010 |
| 7859329 | Configurable clock network for programmable logic device In a programmable logic device having high-speed serial interface channels, a clock distribution network for providing one or more high-speed clocks to dynamic phase alignment circuitry of those high-speed serial interfaces includes at least one bus that is segmenta... | 12/28/2010 |
| 7830205 | Fuse circuit for use in a semiconductor integrated apparatus A fuse circuit of a semiconductor integrated apparatus includes first and second fuse blocks. The first fuse block includes a first up fuse block where a first plurality of fuses are arranged and a first down fuse block where a second plurality of fuses are arranged... | 11/09/2010 |
| 7675357 | Multi-system module having functional substrate A multi-system module having a functional substrate includes a substrate comprising therein at least one control circuit units, and a plurality of main circuit units provided on one side surface of the substrate. The main circuit units are electrically connected to ... | 03/09/2010 |
| 7646237 | Configurable clock network for programmable logic device In a programmable logic device having high-speed serial interface channels, a clock distribution network for providing one or more high-speed clocks to dynamic phase alignment circuitry of those high-speed serial interfaces includes at least one bus that is segmenta... | 01/12/2010 |
| 7642844 | Semiconductor integrated circuit for voltage detection A semiconductor integrated circuit includes a semiconductor substrate, one or more wells formed in the semiconductor substrate, one or more diffusion layers formed in the one or more wells, a plurality of interconnects formed in an interconnect layer, the one or mor... | 01/05/2010 |
| 7557646 | Semiconductor device with non-intersecting power and ground wiring patterns A semiconductor circuit is installed on a printed circuit board having a power wiring pattern and a ground wiring pattern that do not intersect. The semiconductor circuit includes a first power supply terminal and a first ground terminal for a first side of the semi... | 07/07/2009 |
| 7545205 | Low power on-chip global interconnects An apparatus including a first circuit, a second circuit and a third circuit. The first circuit may be configured to (a) receive (i) a plurality of input signals and (ii) a clock signal and (b) present (i) a plurality of low-swing differential signals and (ii) a ful... | 06/09/2009 |
| 7538603 | Signal distribution architecture and semiconductor device Provided is a grid-type high-speed clock signal distribution network capable of reducing a difference in amplitude of a standing wave on a transmission line and of supplying a signal from any position. The network for transmitting the clock signal is such that ends ... | 05/26/2009 |
| 7521993 | Substrate stress signal amplifier A computer system includes a substrate on which a first current mirror and a second current mirror are disposed. When a stress is present, a behavior, e.g., carrier mobility, of at least one of the devices in each of the first current mirror and the second current m... | 04/21/2009 |
| 7508256 | Integrated circuit with signal bus formed by cell abutment of logic cells An integrated circuit with a signal bus formed by the cell abutment of logic cells. The integrated circuit comprises at least two logic cells. The signal bus is formed by cell abutment of the at least two logic cells. The signal bus is configured to receive a signal... | 03/24/2009 |
| 7482861 | Semiconductor integrated circuit device, and method of manufacturing the same A power MOSFET Qp and a protection circuit 3 are formed over a semiconductor substrate to constitute a construction in which the power MOSFET Qp and the protection circuit 3 are electrically separated from each other. Then, a screening voltage is appli... | 01/27/2009 |
| 7479825 | Clock forming method for semiconductor integrated circuit and program product for the method Regions G1 to G8 each including a predetermined number of flip-flops (FF) are divided into two groups. This dividing is performed so that the number of data connection channels intersected by a boundary is minimized. In the case of intersection of two ... | 01/20/2009 |
| 7427886 | Clock generating method and circuit thereof A clock generating method and circuit are provided. The circuit includes a basic clock unit, a plurality of subclock units, which are connected in parallel or in series, and a plurality of special control units (SCU). The basic clock unit provides a basic clock sign... | 09/23/2008 |
| 7394304 | Semiconductor integrated circuit, electronic device using the same, and controlling method of semiconductor integrated circuit A semiconductor integrated circuit comprises a logic circuit unit, a signal control unit, a first signal selecting unit to a third signal selecting unit, and a first element electrode to a fourth element electrode. A part of signal lines of the logic circuit unit is... | 07/01/2008 |
| 7391255 | Semiconductor phase adjustment system module A module includes a semiconductor device, a phase adjustment circuit generating a second clock so that a phase adjustment signal output from the semiconductor device and a first clock have a predetermined phase relationship, and an output circuit that is provided in... | 06/24/2008 |
| 7370134 | System and method for memory hub-based expansion bus A system memory includes a memory hub controller, a memory module accessible by the memory hub controller, and an expansion module having a processor circuit coupled to the memory module and also having access to the memory module. The memory hub controller is coupl... | 05/06/2008 |
| 7366864 | Memory hub architecture having programmable lane widths A processor-based system includes a processor coupled to a system controller through a processor bus. The system controller is used to couple at least one input device, at least one output device, and at least one data storage device to the processor. Also coupled t... | 04/29/2008 |
| 7366920 | System and method for selective memory module power management A memory module includes a memory hub that monitors utilization of the memory module and directs devices of the memory module to a reduced power state when the module is not being used at a desired level. System utilization of the memory module is monitored by track... | 04/29/2008 |
| 7363419 | Method and system for terminating write commands in a hub-based memory system A memory hub receives downstream memory commands and processes each received downstream memory command to determine whether the memory command includes a write command directed to the memory hub. The memory hub operates in a first mode when the write command is dire... | 04/22/2008 |
| 7362093 | IC selectively connecting logic and bypass conductors between opposing pads In a functional mode, the functional core logic of a die is connected to the input and output pads and the die performs its intended function. In a bypass mode, the input and output buffers of the functional core logic are disabled and pad sites of corresponding pos... | 04/22/2008 |
| 7360011 | Memory hub and method for memory system performance monitoring A memory module includes a memory hub coupled to several memory devices. The memory hub includes at least one performance counter that tracks one or more system metrics-for example, page hit rate, number or percentage of prefetch hits, cache hit rate or percentage, ... | 04/15/2008 |
| 7353320 | Memory hub and method for memory sequencing A memory module includes a memory hub coupled to several memory devices. The memory hub includes at least one performance counter that tracks one or more system metrics—for example, page hit rate, prefetch hits, and/or cache hit rate. The performance counter commu... | 04/01/2008 |
| 7348837 | Point diffusion signal distribution with minimized power consumption and signal skew For distributing a signal to loads in an area, the area is divided into a plurality of regions. A respective signal point is disposed in each region for providing the signal to a load in the region. A respective diffusion point is disposed between any two neighborin... | 03/25/2008 |
| 7342414 | Fast router and hardware-assisted fast routing method A fast router and a fast hardware-assisted routing method are disclosed in a network having endpoints, switches and interconnect links. The switches are programmable to allow endpoints to be connected through a particular configuration of switches. The switches also... | 03/11/2008 |
| 7342440 | Current regulator having a transistor and a measuring resistor The invention relates to a current regulator having the following features: a first semiconductor body (1; 1′) having a first and second terminal contact (11, 12), a transistor (T) having a control ... | 03/11/2008 |
| 7336089 | Power line control circuit of semiconductor device A power line control circuit of a semiconductor device in which a width of a power line can be selectively controlled. The power line control circuit of the semiconductor device according to the present invention can selectively control the width of the power line e... | 02/26/2008 |
| 7330992 | System and method for read synchronization of memory modules A memory module includes several memory devices coupled to a memory hub. The memory hub includes several link interfaces coupled to respective processors, several memory controller coupled to respective memory devices, a cross-bar switch coupling any of the link int... | 02/12/2008 |
| 7324364 | Layout techniques for memory circuitry An integrated circuit includes memory circuitry with a number of bit line structures, each including at least three bit lines; a number of word lines that intersect with the bit line structures at a number of sites; and a number of switching devices located at the s... | 01/29/2008 |
| 7321257 | Semiconductor device capable of detecting an open bonding wire using weak current An IC chip has a series regulator built therein. A battery voltage is applied to an input pin. An output of a transistor constituting the series regulator occurs at an output pin via an output pad. A feedback signal derived from an output voltage occurs at an end of... | 01/22/2008 |
| 7312517 | System-in-package type semiconductor device A system-in-package type semiconductor device includes a plurality of semiconductor chips, a first semiconductor chip 1110 to which electric power is supplied from first power supply wiring 1111, and first ground wiring 1112 to which the first c... | 12/25/2007 |
| 7313369 | Communication semiconductor integrated circuit and radio communication system A communication semiconductor integrated circuit has an oscillator circuit forming part of a transmission PLL circuit fabricated on a single semiconductor chip together with an oscillator circuit forming part of a reception PLL circuit and an oscillator circuit for ... | 12/25/2007 |
| 7313715 | Memory system having stub bus configuration A memory system having a stub-bus configuration transmits a free-running clock through the same path as data signals. A single clock domain is employed for both read and write operations. For both operations, the read or write clock signal is routed through the same... | 12/25/2007 |
| 7310748 | Memory hub tester interface and method for use thereof A memory hub including a memory test bridge circuit for testing memory devices. Test command packets are coupled from a tester to the memory hub responsive to a test clock signal having a test clock frequency. The test bridge circuit generates memory device command,... | 12/18/2007 |
| 7310264 | Rectifying charge storage memory circuit A composite rectifying charge storage device, consisting of a rectifier and capacitor which share common elements, is provided in a memory circuit or memory cell. In one form, the memory cell is adapted for alternative operation as a random access memory (RAM) or as... | 12/18/2007 |
