Did You Know...
...that when IBM conducted a market study of Chester Carlson's invention in 1959, the company concluded that it would take only 5000 units of his new product to saturate the market? IBM therefore declined to be part of the new product introduction. Too bad for IBM. Carlson's invention was the xerography process, and his new product was the beginning of the Xerox Corporation. It is estimated that every day, worldwide, 3,000,000,000 copies are made!!
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| Number | Title | Issue Date |
| 8120385 | Reduction in kickback effect in comparators The present disclosure relates to reduction in the effect of kickback in comparators by means of charge injection implemented by means of voltage controlled switches with attributes similar to those of an input differential pair. The voltage controlled switches prod... | 02/21/2012 |
| 8018253 | Sense amplifier circuit and related configuration and operation methods A sense amplifier circuit is provided with a first transistor arrangement comprising a first n-type field effect transistor (NFET) having a respective body node, and a second transistor arrangement comprising a second NFET having a respective body node. The second t... | 09/13/2011 |
| 7906992 | High speed latch comparators In a latch circuit having a bistable pair of cross connected transistors of a first polarity and a third transistor of a second polarity, a current signal greater than a bias current is received at a latch circuit port, amplified with the third transistor, and appli... | 03/15/2011 |
| 7868663 | Receiver circuit for use in a semiconductor integrated circuit A receiver circuit for sensing and transmitting input data in sync with a plurality of clock signals having mutually different phase sequentially enabled comprising a sense amplifier configured to receive, as offset voltages, first signals which can be obtained by a... | 01/11/2011 |
| 7825699 | Receiver circuit having compensated offset voltage A receiver circuit includes an offset control signal generating unit that outputs a plurality of offset control signals using an offset voltage. A sense amplifier receives a first current and a second current generated on the basis of an up input signal and a down i... | 11/02/2010 |
| 7768320 | Process variation tolerant sense amplifier flop design One embodiment of the present invention sets forth a sense amplifier flop design that is tolerant of process variation. Specific staging of signal transitions through the sense amplifier flop circuit eliminate operational phases involving short-circuit currents betw... | 08/03/2010 |
| 7701257 | Data receiver and semiconductor device including the data receiver The invention is directed to data receivers such as those used in semiconductor devices. Embodiments of the invention provide a loop unrolling DFE receiver that uses analog control signals from each equalizer to avoid timing delays associated with the use of latched... | 04/20/2010 |
| 7679405 | Latch-based sense amplifier Various embodiments of the present invention provide systems and circuits for processing information through comparison of input signals. For example, various embodiments of the present invention provide differential latch circuits. Such differential latch circuits ... | 03/16/2010 |
| 7629817 | System and apparatus for aperture time improvement In particular embodiments, an apparatus includes a first transistor connected at the gate to a first input signal voltage and a second transistor connected at the gate to a second input signal voltage. The apparatus further includes a deactivation element coupled to... | 12/08/2009 |
| 7589567 | Compensation technique for current source channel-length modulation A circuit is provided that includes a current source, and a compensation circuit to generate a compensation current based on an output voltage of the current source. The circuit further includes a combiner to combine the compensation current with an output current o... | 09/15/2009 |
| 7482843 | Signal amplifier The amplifier includes first and second inverters that form a flip-flop. In this flip-flop, an input of first inverter is connected to an output of the second inverter, and an output of the first inverter is connected to an input of the second inverter. Control term... | 01/27/2009 |
| 7477076 | Low-voltage, low-power-consumption, and high-speed differential current-sense amplification A differential current-sensing amplifier includes two inverters, two resistors, a NOR gate, and five switches. The first inverter has a first output; the second inverter has a second output. The first resistor is connected between the first inverter and ground; the ... | 01/13/2009 |
| 7443207 | Differential output circuit with stable duty A differential output circuit includes a bias circuit connected with a first voltage. An input circuit section includes first and second MOS transistors of a first conductive type, and the first and second MOS transistors are connected with the first voltage through... | 10/28/2008 |
| 7439775 | Sense amplifier circuit and sense amplifier-based flip-flop having the same A sense amplifier-based flip-flop includes a first latch, a second latch, a floating reduction unit, an input signal applying unit, a ground switch and a delay reduction unit. The first latch outputs a signal to a first output terminal pair, and outputs an evaluatio... | 10/21/2008 |
| 7414908 | Magnetic memory device A Magnetic Random Access Memory (MRAM), in which very little current flows through MTJ elements and very little voltage is applied across them, the MRAM being provided with sense-amplifiers capable of amplifying the potential difference between their corresponding p... | 08/19/2008 |
| 7400279 | Circuits and methods with comparators allowing for offset reduction and decision operations Circuits and methods may be improved by using ADCs that compensate for the effect of comparator input offset on comparator decisions. Offset compensation may be implemented in an ADC by using an amplifier section between the input of the ADC and a comparator section... | 07/15/2008 |
| 7394678 | Over-driven access method and device for ferroelectric memory An over-driven access method and device for ferroelectric memory. When accessing the data stored in a ferroelectric memory, the invention further provides an over-driven current to slightly reduce/raise the voltages in bit lines BL and BL′ to further enlarge the v... | 07/01/2008 |
| 7368955 | Current-balanced logic circuit In accordance with some embodiments, a current-balanced logic circuit includes a first sense amplifier, a second sense amplifier, and a current-source transistor which provides bias current to the first and second sense amplifiers. The first and second sense amplifi... | 05/06/2008 |
| 7352215 | High speed latch comparators In a latch circuit having a bistable pair of cross connected transistors of a first polarity and a third transistor of a second polarity, a current signal greater than a bias current is received at a latch circuit port, amplified with the third transistor, and appli... | 04/01/2008 |
| 7339403 | Clock error detection circuits, methods, and systems Clock error detections circuits can detect clock duty cycle error and/or quadrature phase error. During an evaluation phase, capacitors are charged. During an evaluation phase, the capacitors are unequally discharged based on the error. A positive feedback mechanism... | 03/04/2008 |
| 7339402 | Differential amplifier with over-voltage protection and method Circuitry for preventing damage to bipolar transistors in integrated circuit amplifier circuitry during slew-limited operation includes first and second transistors, each having first, second, and third electrodes, a first one of the first and second electrodes of t... | 03/04/2008 |
| 7327621 | Current sense amplifier with lower sensing error rate by using smaller sensing current difference A sensing amplifier comprising a program cell current sensing circuit, an erase cell current sensing circuit and a latch circuit is provided. Each of the program and erase cell current sensing circuits further comprises a plurality of program/erase memory cells, a f... | 02/05/2008 |
| 7323911 | Differential sense amplifier circuit and method triggered by a clock signal through a switch circuit A differential sense amplifier is described that can be configured as a preamplifier or a latch circuit as triggered by a clock signal connected to a switch circuit. When the clock signal is set at a first signal level, the switch circuit in the differential sense a... | 01/29/2008 |
| 7323923 | Driver circuit A driver circuit is provided for preventing generation of a pass-through current in a CMOS output unit even if a power supply voltage VDD supplied from a low voltage power supply drops below a recommended operating power supply voltage. The driver circuit includes a... | 01/29/2008 |
| 7321504 | Static random access memory cell A static random access memory (SRAM) cell having an inverter and a tri-state inverter. An input of the inverter is coupled to an output of the tri-state inverter and an output of the inverter is coupled to an input of the tri-state inverter. The tri-state inverter h... | 01/22/2008 |
| 7307867 | Over-driven access method and device for ferroelectric memory An over-driven access method and device for ferroelectric memory. When accessing the data stored in a ferroelectric memory, the invention further provides an over-driven current to slightly reduce/raise the voltages in bit lines BL and BL′ to further enlarge the v... | 12/11/2007 |
| 7304879 | Non-volatile memory element capable of storing irreversible complementary data A non-volatile memory element for storing at least one data item, having a readable memory cell which can be written on with a first part of a data item, the memory cell exhibiting a first characteristic which is electrically irreversibly modifiable according to the... | 12/04/2007 |
| 7304903 | Sense amplifier circuit A sense amplifier circuit includes a first double-gate metal oxide semiconductor field effect transistor (DGMOSFET) having a first gate defining a first input to the circuit, a second gate and an output being coupled to a first output of the circuit and a second DGM... | 12/04/2007 |
| 7304527 | Fuse sensing circuit A sensing circuit senses the programmed state of fuses such as polysilicon (poly) fuses. In a preferred embodiment, the sensing circuit comprises first and second amplifier stages, a fuse and a reference resistor wherein the fuse and the reference resistor are conne... | 12/04/2007 |
| 7301373 | Asymmetric precharged flip flop A flip-flop circuit includes a differential stage coupled to a latch stage. The differential stage comprises cross-coupled dynamic logic and only provides a single output to the latch stage. During an evaluation phase, the state of a data input signal is sensed. Dep... | 11/27/2007 |
| 7295043 | Differential output circuit for improving bandwidth A differential output circuit includes first and second inputs, first and second outputs, a resistor element connected between the outputs, first and second N-channel MISFETs, and first and second P-channel MISFETs. The inputs respectively receive first and second c... | 11/13/2007 |
| 7279939 | Circuit for differential current sensing with reduced static power Returning to FIG. 2, sense circuit 201 represents the circuit that must sense the signaling on an interconnect. NMOS device 202 is always on so that there is a continuous path to ground whenever PMOS driver 204 is on. Since leakage power ... | 10/09/2007 |
| 7274259 | Layout structure of signal driver Disclosed herein is a layout structure of a signal driver. The layout structure of the signal driver of the present invention includes a first signal response unit, a second signal response unit, and a current source unit. The first signal response unit responds to ... | 09/25/2007 |
| 7271639 | Voltage level converter circuit and semiconductor integrated circuit device Differential signals are supplied to gates of first and second transistors. One end and a gate of a third transistor are connected to a signal output node. One end and a gate of a fourth transistor are connected to the other end of the second transistor. A fifth tra... | 09/18/2007 |
| 7262638 | Current sense amplifier A current sense amplifier includes a pair of cross-coupled transistors, each transistor being connected between a respective input signal line and a respective output signal generating node, for amplifying voltage difference between the output signal generating node... | 08/28/2007 |
| 7262639 | High-speed comparator A differential comparator with improved bit-error rate performance operating with a low supply voltage. The differential comparator includes a first pair of transistors receiving a differential input. A second pair of transistors is coupled to the first pair of tran... | 08/28/2007 |
| 7263016 | Method and system for pre-charging and biasing a latch-type sense amplifier A method and system for pre-charging and biasing a latch-type sense amplifier are described. According to an embodiment of the invention, the data latch portion of the latch-type sense amplifier includes two cross-coupled inverters having two output nodes, and two i... | 08/28/2007 |
| 7260014 | Voltage supply circuit for memory array programming According to one exemplary embodiment, a memory array includes a number of bitlines. The memory array further includes a voltage supply circuit, where the voltage supply circuit is configured to receive an operating voltage and a control signal and to output a low o... | 08/21/2007 |
| 7257042 | Enhanced sensing in a hierarchical memory architecture A sense amplifier circuit for sensing a logic state of a selected memory cell in a memory circuit includes a precharge circuit and a latch circuit. The precharge circuit is adapted for connection to a pair of complementary bit lines corresponding to the selected mem... | 08/14/2007 |
| 7242239 | Programming and determining state of electrical fuse using field effect transistor having multiple conduction states A circuit is provided which is operable to program an electrically alterable element, e.g., fuse or antifuse, to a programmed state and determine whether the electrically alterable element is in the programmed state or not. Such circuit includes a multiple conductio... | 07/10/2007 |
