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| Number | Title | Issue Date |
| 7427879 | Frequency detector utilizing pulse generator, and method thereof The present invention discloses a frequency detecting apparatus for detecting a frequency of an input clock. The frequency detecting apparatus includes: a pulse generator, a digital signal generator, and a decoder. The pulse generator is coupled to the input clock f... | 09/23/2008 |
| 7375557 | Phase-locked loop and method thereof and a phase-frequency detector and method thereof The phase-frequency detector may include a first flip-flop configured to generate a first signal, the first signal transitioning to a first logic level in response to a first edge of a first input signal and transitioning to a second logic level in response to a del... | 05/20/2008 |
| 7375565 | Delay locked loop in semiconductor memory device A delayed lock loop for preventing a stuck fail in a dead-zone includes a clock buffering block for generating a first and a second internal clock signals; a phase comparison block for delaying a feedback signal by a first predetermined value and for respectively co... | 05/20/2008 |
| 7327171 | Charge pump clock for non-volatile memories A charge pump clock circuit for a memory device generates pump clock signals at an adaptive rate. Clock edges are generated at a minimum of TD seconds apart so long as address transitions do not exceed a pre-determined limit. However, if address changes a... | 02/05/2008 |
| 7319350 | Lock-detection circuit and PLL circuit using same A lock-detection circuit that can set an acceptable phase-error range adapted to define a locked state and/or an unlocked state at a constant rate without being affected by a frequency and that can detect the locked state and/or the unlocked state with precision wit... | 01/15/2008 |
| 7292070 | Programmable PPM detector A device such as a programmable logic device (“PLD”) includes circuitry for detecting the PPM frequency difference between two input clock signals. For example, this circuitry may accept a user-programmable PPM threshold value and output a signal when this thres... | 11/06/2007 |
| 7288979 | Semiconductor equipment There is provided a semiconductor integrated circuit in which a source clock (S101) is inputted to a delay circuit (3), a counter circuit (6) is operated in response to a delay clock (S102) which is the output of the delay circuit (3 | 10/30/2007 |
| 7265637 | Startup/yank circuit for self-biased phase-locked loops An apparatus for controlling a phase-locked loop includes a detector for detecting at least one of a startup condition and a yank condition and a controller for controlling current between a charge pump and the phase-locked loop. If a startup condition is detected, ... | 09/04/2007 |
| 7259595 | Circuit and method for detecting frequency of clock signal and latency signal generation circuit of semiconductor memory device with the circuit A frequency detection circuit and method of detecting the frequency of a clock signal, and a latency signal generation circuit for a semiconductor memory device that includes the frequency detection circuit. The frequency detection circuit includes a frequency detec... | 08/21/2007 |
| 7224639 | Multi-phase clock signal generator and method having inherently unlimited frequency capability A delay-lock loop includes several delay lines, all but the first of which is composed of at least one variable delay unit that provides a fixed delay and a variable delay. The first delay line is composed of a plurality of fixed delay units, but no variable delay u... | 05/29/2007 |
| 7148755 | System and method to adjust voltage A system and method that can be utilized to implement voltage adjustment (e.g., for an integrated circuit). In one embodiment, the system comprises a frequency generator that provides a clock signal having a frequency that varies based on an operating voltage. The s... | 12/12/2006 |
| 7145398 | Coarse frequency detector system and method thereof An improved coarse frequency detector includes a first storage device responsive to a data signal and a sub-multiple of a clock signal for detecting a first transition in the data signal during a predetermined state of the sub-multiple of the clock signal and genera... | 12/05/2006 |
| 7106655 | Multi-phase clock signal generator and method having inherently unlimited frequency capability A delay-lock loop includes several delay lines, all but the first of which is composed of at least one variable delay unit that provides a fixed delay and a variable delay. The first delay line is composed of a plurality of fixed delay units, but no variable delay u... | 09/12/2006 |
| 7103130 | Phase-locked loop circuit Method and circuitry for improving the accuracy and efficiency of a phase-locked loop. More specifically, the present invention relates to a method and device for monitoring the frequency discrepancy between two signals in conjunction with at least one data signal s... | 09/05/2006 |
| 7095289 | Yank detection circuit for self-biased phase locked loops An apparatus for controlling a phase-locked loop includes a detector for detecting at least one of a startup condition and a yank condition and a controller for controlling current between a charge pump and the phase-locked loop. If a startup condition is detected, ... | 08/22/2006 |
| 7084681 | PLL lock detection circuit using edge detection and a state machine A lock detection circuit operatively associated with a phase-locked loop indicates when a feedback clock signal is locked to a reference clock signal. The lock detection circuit counts the number of rising and falling edges of the feedback clock signal that are dete... | 08/01/2006 |
| 7049852 | Fractional-integer phase-locked loop system with a fractional-frequency-interval phase frequency detector A phase-locked loop circuit has a fractional-frequency-interval phase frequency detector, a charge pump, an oscillator, and a divider. The fractional-frequency-interval phase frequency detector has a phase frequency detector unit that is utilized as or comprises a p... | 05/23/2006 |
| 7038508 | Methods and apparatuses for detecting clock loss in a phase-locked loop Embodiments of the present invention describe methods and apparatuses for detecting signal loss in circuits such as a phase-locked loop (PLL). In one embodiment a PLL is equipped with detection logic to detect loss of a reference clock provided to the PLL and a feed... | 05/02/2006 |
| 7038496 | Device for comparison of frequencies with low temporal inertia The present invention relates to a device for comparison CMP, which is designed to emit a control signal Vcnt, which is representative of a difference which exists between the input signal frequencies Vdiv and Vref. The device according to the invention includes a p... | 05/02/2006 |
| 7020819 | Semiconductor integrated circuit with local monitor circuits A semiconductor integrated circuit includes a boundary scan register and a plurality of local monitor circuits. The local monitor circuits are arranged individually about peripheral circuit regions of a semiconductor integrated circuit, being spaced from the boundar... | 03/28/2006 |
| 7015727 | Generating a lock signal indicating whether an output clock signal generated by a PLL is in lock with an input reference signal A PLL lock generator using one circuit (lock detection block) to indicate whether an output clock signal is locked to an input reference signal, and another circuit to determine whether the signals are out-of-lock. A lock generation blocks examines several indicatio... | 03/21/2006 |
| 6960940 | Short circuit protection apparatus with self-clocking self-clearing latch A latch for detecting a state transition of an input signal and generating a self-clearing reset signal on an output. The latch comprises: 1) a transfer gate for passing the input signal to a first node when the input transfer gate is enabled; 2) a transition detect... | 11/01/2005 |
| 6949960 | Semiconductor integrated circuit comprising functional modes An integrated circuit device includes a pin for receiving a DC voltage component signal. The device includes a signal source for applying an AC signal to the pin, a buffer for converting the AC signal into a digital signal, and a digital detector for detecting a fre... | 09/27/2005 |
| 6834093 | Frequency comparator circuit A frequency comparator circuit is configured to compare whether the frequency of two input signals are within a tolerance of each other. The frequency comparator circuit includes two counter circuits, an AND gate, and a frequency detector circuit that is configured ... | 12/21/2004 |
| 6831485 | Phase frequency detector with a narrow control pulse A phase frequency detector with a narrow control pulse comprises mainly two substantially equivalent phase latches with a narrow control pulse, and a reset signal generating unit. Each phase latch of a narrow control pulse has a clock pulse input end and a signal ou... | 12/14/2004 |
| 6731139 | Short circuit protection apparatus with self-clocking self-clearing latch A latch for detecting a state transition of an input signal and generating a self-clearing reset signal on an output. The latch comprises: 1) a transfer gate for passing the input signal to a first node when the input transfer gate is enabled; 2) a transition detect... | 05/04/2004 |
| 6704382 | Self-sweeping autolock PLL An improved phase-lock loop circuit comprising a phase detector, a loop filter, and a voltage controlled oscillator. The phase detector samples the phase-lock loop input signal at various points in a cycle of the phase-lock loop output signal and outputs ... | 03/09/2004 |
| 6650146 | Digital frequency comparator A digital frequency comparator includes two double-edge triggered flip-flops and a combination logic. Each of the double-edge triggered flip-flops includes two D-type flip-flops and two multiplexers. The first D-type flip-flop receives a first reference c... | 11/18/2003 |
| 6466058 | PLL lock detection using a cycle slip detector with clock presence detection A system 400 and method 1400 are disclosed for a lock detection circuit of a phase locked loop used in a communications device. The lock detection circuit includes a cycle slip detector and a clock presence detector. The cycle slip detector receives a ref... | 10/15/2002 |
| 6404240 | Circuit and method of a three state phase frequency lock detector A three state phase frequency lock detector (14) is provided which monitors the UP and DOWN phase pulses generated by a three state phase frequency detector (PFD). The lock detector (14) asserts the lock detect signal when the rising edges of the UP and D... | 06/11/2002 |
| 6331792 | Circuit and method for unlimited range frequency acquisition An improved frequency detector circuit and method is disclosed for frequency acquisition. The frequency detector is particularly useful as part of a frequency loop in a standard two loop clock and data recovery (CDR) circuit because, for among other reaso... | 12/18/2001 |
| 6320424 | Method of providing and circuit for providing phase lock loop frequency overshoot control A phase lock loop system is provided that includes a phase frequency detector device to receive a reference clock signal and a feedback clock signal and to provide a first control signal and a second control signal. The phase lock loop system may include ... | 11/20/2001 |
| 6259279 | High frequency detection circuit and method The present invention is a high frequency detection circuit (10) which includes a high frequency filter (12) and a frequency comparator (14) which compares the output of the high frequency filter with the incoming clock signal to determine if the high fre... | 07/10/2001 |
| 6252428 | Method and apparatus for detecting a sinusoidal signal A method and apparatus for detecting a sinusoidal signal samples a received signal. An error signal generator receives at its inputs two previous samples of the signal and a current sample of the signal and generates an error signal based on these previou... | 06/26/2001 |
| 6177813 | Low frequency detection circuit An improved low frequency detection circuit is disclosed. The low frequency detection circuit employs as an internal clock signal of the system the negative delay signal CK1 generated in accordance with the negative delay signal generator when the externa... | 01/23/2001 |
| 6114880 | Dynamic over frequency detection and protection circuitry An over frequency detection circuit which is based on the concept of a critical path in a design to protect an IC chip from running at a rate which will produce unpredictable results. The over frequency detection circuit will compare the output of a criti... | 09/05/2000 |
| 6084442 | Digital oscillator for generating two fixed pulse signals from one clock In order to use a digital oscillator to generate a target frequency ZT with a "high" or "low" level constant in time from a working clock by variable division by a first division factor, two divider circuits which can be respectively triggered by the posi... | 07/04/2000 |
| 6081137 | Frequency detecting circuit A frequency detecting circuit is provided that includes a level shift detecting unit for generating pulse signals of a certain pulse width at each level shifting of input clock signals and a level detecting unit. The level detecting unit includes a chargi... | 06/27/2000 |
| 6075389 | Operation speed measuring circuit and semiconductor device incorporating the same circuit An operation speed measuring circuit measures a difference in propagation delay time between first and second path 2, 3 including logic gates connected in series and thus confirms that an element provided on a chip obtains a specified operation speed. Thi... | 06/13/2000 |
| 6069498 | Clock generator for CMOS circuits with dynamic registers An apparatus has a clock monitoring device, which determines whether or not the clock rate of an input clock signal (.PHI.0) has fallen below a predetermined minimum clock rate. A system is provided which, from the input clock signal, forms a m... | 05/30/2000 |
