Bizarre Patents
Wearable Device For Feeding and Observing Birds and Other Flying Animals
A device for feeding and observing flying animals comprising a hat, a support mounted on the hat and extending outward from the hat, and a feeder mounted on the support.
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| Number | Title | Issue Date |
| 8085081 | Semiconductor device for output of pulse waveforms A semiconductor device has multiple high-side field-effect transistors and multiple low-side field-effect transistors connected to a single output terminal to generate an output signal. A driver circuit outputs driving signals that turn the field-effect transistors ... | 12/27/2011 |
| 7755413 | Combination of analog and digital feedback for adaptive slew rate control An apparatus for scaling a load device with frequency in a phase interpolator can include an analog loop and a digital loop. The load device of the phase interpolator can include a transistor and a plurality of resistors selectively configured in parallel with the t... | 07/13/2010 |
| 7386773 | Method and system for testing distributed logic circuitry A testing procedure for distributed logic circuits that incorporates an efficient utilization of flip-flops to toggle detect for sensing output is discussed. The distributed logic circuit is a phase interpolator or a phase interpolator preceded by a DLL. The testing... | 06/10/2008 |
| 7352222 | Clock generator with programmable non-overlapping-clock-edge capability A system and method for generating and optimizing clock signals with non-overlapping edges on a chip using a unique programmable on-chip clock generator. Overlapping of the edges of the clocking signals is avoided by adjusting an amount of delay introduced in the on... | 04/01/2008 |
| 7332950 | DLL measure initialization circuit for high frequency operation A memory device, delay lock loop circuit (DLL) and DLL reset circuitry are described. The DLL includes a shift register and a measured delay for pre-loading the shift register. The reset circuitry selectively filters a clock signal propagation through the measured d... | 02/19/2008 |
| RE40053 | Delay circuit having delay time adjustable by current A delay circuit includes a delay part delaying a signal by a delay time which can be varied based on a control current, and a control current adjustment circuit adjusting the control current so that the delay time changes linearly based on a variation in a resistanc... | 02/12/2008 |
| 7239495 | Output circuit with transistor overcurrent protection When the overcurrent detection circuit detects that a voltage drop of the output transistor exceeds a threshold value, it turns on the switch by the first operational amplifier. In the shut-down signal generation circuit, the capacitor is charged with a charge curre... | 07/03/2007 |
| 7127015 | Digital filter for reducing voltage peaks The present invention relates to a digital filter suitable for receiving a digital input signal (INPUT(G)) comprising a voltage peak also known as glitch (G). It is characterized in that it comprises: a delay line (T) adapted to produce a delayed digita... | 10/24/2006 |
| 7120053 | Semiconductor intergrated circuit device with a main cell array and a fuse cell array whose word lines and bit lines are extended in the same directions A semiconductor integrated circuit device includes a main cell array, a fuse cell array, main cell word lines arranged at the main cell array, and fuse cell word lines arranged at the fuse cell array. The fuse cell word lines are formed in a same direction as a dire... | 10/10/2006 |
| 7100067 | Data transmission error reduction via automatic data sampling timing adjustment A data transmission error reduction circuit is formed including a delay circuit, a detection circuit and a control circuit. In one embodiment, the delay circuit includes n delay element and multiplexor pairs, selectively employable to apply an aggregate amount of ti... | 08/29/2006 |
| 7100066 | Clock distribution device and method in compact PCI based multi-processing system Disclosed is a clock distribution device and method in a compact PCI system based multi-processing system. A compact PCI based multi-processing system preferably includes processing signals upon mounting various circuit boards on multiple slots, even if the location... | 08/29/2006 |
| 7061810 | Erasing flash memory without pre-programming the flash memory before erasing An erase operation in a flash memory device includes applying an erase pulse to memory cells of the flash memory device to convert the contents of the memory cells into logic 1 bits before any pre-programming operation is performed. ... | 06/13/2006 |
| 7061811 | Faster method of erasing flash memory An erase operation in a flash memory device includes applying an erase pulse to memory cells of the flash memory device to convert the contents of the memory cells into logic 1 bits before any pre-programming operation is performed. ... | 06/13/2006 |
| 7057444 | Amplifier with accurate built-in threshold Various embodiments of a voltage level detector implemented as an integrated circuit whose trip point is approximately constant over variations in temperature as well as variations in transistor fabrication parameters are disclosed along with a differential amplifie... | 06/06/2006 |
| 7042274 | Regulated sleep transistor apparatus, method, and system A transistor may operate as a sleep transistor or as a regulator. ... | 05/09/2006 |
| 7035148 | Output driver capable of controlling slew rate of output signal according to operating frequency information or CAS latency information An output driver effectively controls the slew rate of an output signal according to CAS latency information including frequency information of an operating clock signal or according to frequency information obtained by detecting the frequency of the operating clock... | 04/25/2006 |
| 6972606 | Delay circuits and related apparatus for extending delay time by active feedback elements A delay circuit and related apparatus for providing a longer delay time, such that when a level of an input signal changes, a level of an output signal changes accordingly after the predetermined delay time. The delay circuit has a storage unit, a current generator,... | 12/06/2005 |
| 6937084 | Processor with dual-deadtime pulse width modulation generator A processor that has pulse width modulation generation circuitry that provides an improved ability to deal with the less than perfect switching characteristics of external switching devices that are connected to PWM hardware included in a processor. Complementary PW... | 08/30/2005 |
| 6937085 | Sense amplifier based voltage comparator The voltage comparator of the present invention comprises a sense amplifier connected to a latch. The sense amplifier has a first input terminal for connecting to the input voltage under consideration and a second input terminal for connecting to the reference volta... | 08/30/2005 |
| 6903974 | Flash memory device with a variable erase pulse A method of operating a flash memory device according to an embodiment of the present invention includes selecting a flash cell in a flash memory device to undergo an erase, applying a long erase pulse to the flash cell, and reading the flash cell. For each time the... | 06/07/2005 |
| 6614275 | Adjustable capacitances for DLL loop and power supply noise filters A delay locked loop having an adjustable capacitance stage is provided. The adjustable capacitance stage facilitates a selective post-silicon adjustment of capacitance amounts between a DLL loop filter capacitance and a power supply noise filter capacitan... | 09/02/2003 |
| 6574154 | Data transmitter A large difference in the lengths of the passages or a large difference in the load capacitances inclusive of parasitic elements of parallel data wirings can cause differences in the propagation time of data on the parallel data wirings. The invention pro... | 06/03/2003 |
| 6535408 | Power converter with adjustable output voltage An adjustable output voltage power converter. The power converter has a positive voltage output terminal, a negative voltage output terminal, a voltage comparator, a voltage shift resistor and a current source. The voltage comparator has a first input ter... | 03/18/2003 |
| 6518800 | System and method for reducing timing mismatch in sample and hold circuits using the clock The present invention relates to a high speed sample and hold circuit which comprises a plurality of sample and hold subcircuits coupled in parallel between an input and an output. The circuit also comprises a calibration circuit coupled to the plurality ... | 02/11/2003 |
| 6518791 | Gate driver for driving a switching element, and a power converter in which the gate driver and an output element are integrated in one-chip A gate driver includes an edge detection circuit, an ON pulse generation circuit, first and second OFF pulse generation circuit and a status hold circuit. The first OFF pulse generation circuit generates a first OFF pulse in response to a leading or trail... | 02/11/2003 |
| 6469557 | Semiconductor integrated circuit and delayed clock signal generation method An object of the present invention is to simply and rapidly adjust a delay time of a delayed clock signal in accordance with a change in frequency of an input clock signal. The present invention comprises: a pulse generating circuit for generating a pulse... | 10/22/2002 |
| 6459319 | Variable delay circuit and semiconductor integrated circuit having the same The variable delay circuit has a delay circuit and a selector. The delay circuit is formed of a plurality of delay stages connected in cascade. The delay circuit receives an input signal at the initial delay stage and respectively outputs a delayed signal... | 10/01/2002 |
| 6373301 | Fast-locking dual rail digital delayed locked loop This present invention discloses a circuit for generating a delay signal, which includes a first delay line for generating a first delay signal, a second delay line for generating a second delay signal, a delay unit for generating an internal delay signal... | 04/16/2002 |
| 6373303 | Sync signal generating circuit provided in semiconductor integrated circuit A sync signal generating circuit has a first I/O replica for delaying an external clock signal, a comparator replica with a variable delay time for delaying an output of the first I/O replica, a first ramp-voltage generating circuit for outputting a first... | 04/16/2002 |
| 6188266 | Electrical signal delay circuit By utilizing a plurality of charge storing elements, a delay circuit may be reduced in size and cost. A delayed output signal is produced a predetermined time period after detection of an input signal by selectively charging and discharging each of a plur... | 02/13/2001 |
| 6157236 | Parametric tuning of an integrated circuit after fabrication The present invention provides an apparatus and method for repairing or improving the behavior of a tunable circuit of an integrated circuit (IC) when a target parameter exceeds a predetermined range due to a design and/or fabrication problem. The tunable... | 12/05/2000 |
| 6097231 | CMOS RC equivalent delay circuit An RC equivalent delay circuit includes an input node, an output node, a feedback node, and an intermediate node; a first inverter having an input coupled to the input node and an output coupled to the intermediate node; a second inverter having an input ... | 08/01/2000 |
| 6094086 | High drive CMOS output buffer with fast and slow speed controls An output buffer is provided which receives an input signal and drives an output terminal. The output buffer has a first driver and a second driver for driving the output terminal to a voltage level corresponding to a logic value of the input signal. The ... | 07/25/2000 |
| 6052016 | Charge and discharge control circuit A plurality of combinations of overcurrent detection voltages and delay times are set in a charge and discharge control circuit. Accordingly, a charge and discharge control circuit is formed in which an overcurrent condition having unexpectedly large cons... | 04/18/2000 |
| 6020775 | Adjustable timer circuit An adjustable timer circuit capable of producing accurate pulse outputs having a wide range of periods. The timer circuit includes a timing capacitor and an associated current source for producing a reference current having a magnitude which is derived fr... | 02/01/2000 |
| 5973526 | Compensating a characteristic of a circuit A method and apparatus is described for compensating circuits. A different locked loop circuit is placed adjacent to a different one of each of the circuits to be compensated. A periodic signal is distributed to each of the locked loop circuits, and each ... | 10/26/1999 |
| 5955910 | Switch with programmable delay A programmable delay circuit employs a comparator to control an output driver. The comparator compares a ramp signal to an error control signal derived from an error amplifier or in the alternative to a disable signal. The output of the comparator is latc... | 09/21/1999 |
| 5939950 | Voltage controlled oscillator having a controllable duty cycle The voltage controlled oscillator comprising a ring oscillator generates an oscillating signal of which the duty cycle is almost 50% in spite of providing a high frequency signal. Each of the delay inverting circuits in the ring oscillator increases the o... | 08/17/1999 |
| 5850159 | High and low speed output buffer with controlled slew rate An output buffer is provided which receives an input signal for output onto an output terminal. The output buffer has a first driver and a second driver for driving the output terminal to a voltage corresponding to a logic value of the input signal. The s... | 12/15/1998 |
| 5841313 | Switch with programmable delay A programmable delay circuit employs a comparator to control an output driver. The comparator compares a ramp signal with a disable signal or an error control signal derived from an error amplifier. The comparator latches the output on until a reset signa... | 11/24/1998 |
