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| Number | Title | Issue Date |
| 7924083 | Isolation circuit An isolation circuit is provided. The isolation circuit is coupled to an output and an input node and includes a first set, a second switch set, and a body bias voltage generator. The first switch set couples a switch control node to a second voltage when a first vo... | 04/12/2011 |
| 7834677 | Transmission gate with body effect compensation circuit A transmission gate circuit includes a first PMOS device, a first NMOS device, a second PMOS device, a second NMOS device, and a third transistor. A gate electrode, a first electrode and a second electrode of the first PMOS device are coupled to a first control sign... | 11/16/2010 |
| 7760006 | Method and system to reduce electromagnetic radiation from semiconductor devices Reducing electromagnetic radiation from semiconductor devices. At least some of the illustrative embodiments are methods comprising driving a Boolean state to a signal pad of a semiconductor device (the driving through a transistor with a first drain-to-source imped... | 07/20/2010 |
| 7385439 | Analog switch having a minimized external flow of leakage current and switched capacitor filter incorporating the analog switch An analog switch used in a switched capacitor filter has N-channel and P-channel MOS FETs connected in parallel between input and output switch terminals, with capacitor charge currents being periodically produced from the output terminal. The filter derives an outp... | 06/10/2008 |
| 7375574 | Semiconductor device A semiconductor device includes a differential level converter circuit that receives a first signal and outputs a second signal of greater amplitude. The differential level converter has a first MISFET pair for receiving the first signal, a second MISFET pair for en... | 05/20/2008 |
| 7368969 | Level shift circuit and semiconductor device A level shift circuit including a capacitor, a charge control circuit, and a limiting circuit. The charge control circuit is connected to the capacitor to provide the voltage of a high potential power supply to the capacitor and to control the charging of the capaci... | 05/06/2008 |
| 7355453 | Techniques for trimming drive current in output drivers Techniques are provided for trimming drive current in output drivers to compensate for process variations, model inaccuracies, and/or an off-target process. The actual output drive current is measured on the integrated circuit (IC) at wafer sort or during a final te... | 04/08/2008 |
| 7348809 | Input buffer In one embodiment, the present invention includes an input buffer with a common gate amplifier having input terminals coupled to receive an incoming common mode voltage. The common gate amplifier may be configured to receive the incoming common mode voltage over a w... | 03/25/2008 |
| 7332941 | Analog switch circuit and sample-and-hold circuit including the same First and second analog switches are connected in series between first and second nodes. One terminal of a third analog switch is connected to a series connection node of the first and second analog switches. The other terminal of the third analog switch is supplied... | 02/19/2008 |
| 7321256 | Highly reliable and zero static current start-up circuits A bandgap reference voltage circuit includes a bandgap circuit, a start-up circuit, and a recovery circuit. Upon device power-on, the start-up circuit provides a start-up current to initialize the bandgap circuit to a valid state, during which the bandgap circuit ge... | 01/22/2008 |
| 7304530 | Utilization of device types having different threshold voltages A technique implements high impedance nodes using high threshold voltage devices that may generate less leakage current and may have a higher gate oxide breakdown voltage than standard devices in a particular manufacturing technology. Under at least one operating co... | 12/04/2007 |
| 7304505 | Output buffer stage The output buffer stage includes a half-bridge output stage having a first pair of complementary drivers connected in series between a supply line and a ground node, the high impedance state or conduction state of which is determined through a pair of control phases... | 12/04/2007 |
| 7304526 | Switching circuit for handling signal voltages greater than the supply voltage Analog bidirectional switches (20) comprising a first (1) and a second (2) transistor function badly in case of the signal voltage at an input or an output of the switch (20) exceeding the supply voltage used for operating the switch (... | 12/04/2007 |
| 7292068 | Output driver for use in semiconductor device There is provided an output driver for use in a semiconductor device capable of remarkably improving linearity of impedance by reducing or minimizing a change of an impedance for output data caused due to a change of an external power supply. The output driver for o... | 11/06/2007 |
| 7279933 | Output driver circuit The present invention relates to an output driver circuit for a semiconductor memory device, in particular, a memory device using a DDR II concept or a concept similar thereto, which can reduce a variation in the slew rate of an output driver thereof between maximum... | 10/09/2007 |
| 7262637 | Output buffer and method having a supply voltage insensitive slew rate An output buffer includes a final driver formed by first and second MOSFET transistors that alternately couple an output terminal to respective supply voltages. The output terminal is biased to a bias voltage intermediate the supply voltages. The slew rate at which ... | 08/28/2007 |
| 7262650 | Amplitude adjusting circuit An amplitude adjusting circuit comprises a first current mirror where a variable current of a variable current source is copied into each of 1st-3rd transistors; a second current mirror where the variable current is copied into each of 11th-13th transistors; a third... | 08/28/2007 |
| 7256625 | Combined output driver A combined output driver for TMDS signals and LVDS signals. A first output driver includes a first differential unit generating a first differential according to first input signals in a first mode and a first clamping device coupled between the first node and the f... | 08/14/2007 |
| 7236019 | Low current wide VREF range input buffer A low-current input buffer is disclosed. The buffer uses self-biased N and P channel differential pairs with their outputs tied together. The self-biasing assists in reducing current consumption. The combination of N and P-channel differential pairs results in symme... | 06/26/2007 |
| 7236021 | Method of controlling slope and dead time in an integrated output buffer with inductive load A method and apparatus independently controls the increasing rate and the decreasing rate a P-channel power FET and an N-channel power FET driving an inductive load. Circuits inhibit turning ON the P-channel FET until the voltage on the gate of the N-channel FET fal... | 06/26/2007 |
| 7230463 | Method and apparatus for controlling transition rates on adjacent interconnects A method, and apparatus are provided for controlling transition rates on adjacent interconnects in an electronic chip design. Each interconnect includes a first inverter that receives a net input and provides an initial inverted output and a second inverter coupled ... | 06/12/2007 |
| 7230457 | Programmable dual drive strength output buffer with a shared boot circuit An integrated circuit device is discussed that includes a data output driver having two modes of operation for driving a data bus. The output driver includes a circuit to produce a full drive output high signal, a partial drive output high signal, a full drive outpu... | 06/12/2007 |
| 7205837 | Body effect amplifier A circuit includes a transistor having a biased gate terminal and an input coupled to a bulk terminal. A voltage applied between the bulk terminal and the source terminal modulates the drain-source current. The transistor operates in a saturation region with a bias ... | 04/17/2007 |
| 7183816 | Circuit and method for switching an electrical load on after a delay A circuit (S1) for switching on an electrical load which can be connected downstream from the circuit comprises a first electronic switching means (T1) in a first path, and a second electronic switching means (T2) in a second path, which is in p... | 02/27/2007 |
| 7183792 | Method and system for detecting a mode of operation of an integrated circuit, and a memory device including same A threshold detection circuit for developing a mode trigger signal includes an input that receives an input signal. In response to the input signal having approximately an input threshold value for a triggering time, the threshold detection circuit activates the mod... | 02/27/2007 |
| 7176728 | High voltage low power driver A power driver circuit is provided including a low voltage source, a high voltage source, at least one input signal line, an output node, and circuitry adapted to connect the output node to the low voltage source when the input signal line is in a first state and to... | 02/13/2007 |
| 7164304 | Duty ratio correction circuit A duty ratio correction circuit includes: a first switching amplifier circuit into which an input pulse signal is input; a current control device connected with the switching device for controlling a current in accordance with a bias voltage signal; a waveform shapi... | 01/16/2007 |
| 7138846 | Field effect transistor switch circuit A field effect transistor switch circuit may include: (1) first, second, and third switch terminals; (2) a first field effect transistor, a pair of the main electrodes of which are connected respectively to the first switch terminal and the second swit... | 11/21/2006 |
| 7126409 | Three level inverter The present invention relates to a high efficiency three-level inverter apparatus containing both bipolar and field effect transistors. An embodiment of a modified control scheme is also presented whereby transistors are modulated differently for each quadrant of ou... | 10/24/2006 |
| 7126394 | History-based slew rate control to reduce intersymbol interference In one aspect of the invention, a method of reducing intersymbol interference on a signal line is disclosed. A state machine records previous bits that were transmitted over the line. If the bit on the line has been static for several clock cycles, the slew rate wil... | 10/24/2006 |
| 7126389 | Method and apparatus for an output buffer with dynamic impedance control A method and apparatus for an output buffer with dynamic impedance control have been disclosed. ... | 10/24/2006 |
| 7126378 | High speed signaling system with adaptive transmit pre-emphasis A signaling system having first and second sampling circuits and an output driver circuit. The first sampling circuit samples a first signal generated by the output driver circuit to determine whether the first signal exceeds a first threshold. The second sampling c... | 10/24/2006 |
| 7088125 | Reducing coupling noise in an output driver An output driver may reduce coupling noise. The output driver may include a first transistor, a second transistor, and/or a noise-eliminating portion. The first transistor may have a first terminal connected to a first voltage, a second terminal connected to a first... | 08/08/2006 |
| 7075356 | Charge pump circuit According to the charge pump circuit, a constant current charging and discharging circuit using follower circuits is interposed at current paths in charging and discharging a capacitor for stepping up. Transistors of the follower circuits are alternately made ON in ... | 07/11/2006 |
| 7075343 | Self-timed switching regulator pre-driver A switching voltage regulator includes a switching transistor connected to conduct a current (i) between a supply voltage and a first node in response to a control signal which cycles the transistor on and off, and a “pre-driver” circuit which provides the contr... | 07/11/2006 |
| 7071758 | Voltage level shifter A voltage level shifter is provided. The shifter includes an AND gate for generating a synchronizing signal according to a periodic signal and a primitive input signal. The synchronizing signal and a first periodic control signal that are in phase with the periodic ... | 07/04/2006 |
| 7068077 | LVDS output driver having low supply voltage capability A LVDS output driver has been disclosed. One embodiment of the LVDS output driver includes a number of source followers, each of the source followers including a pull-down transistor having a source, a drain, a gate, and a bulk terminal. The embodiment of the LVDS o... | 06/27/2006 |
| 7064596 | Reducing crowbar current in a latch hysteresis receiver One embodiment of the present invention provides a latch hysteresis receiver circuit having reduced crowbar current. Within the present embodiment, the latch hysteresis receiver circuit comprises an input stage and a latch hysteresis switching element coupled to the... | 06/20/2006 |
| 7064598 | Radio frequency CMOS buffer circuit and method A buffer (40) includes a capacitor (42) having a first terminal for receiving an input signal, and a second terminal; a first transistor (44) having a first current electrode for receiving a first power supply voltage, a control electrode couple... | 06/20/2006 |
| 7064599 | Apparatus and method for signal transmission A signal transmission gate includes a switch such as a transistor. The switch includes a gate terminal adapted to receive a control voltage, and a source terminal and a drain terminal. One of the source and drain terminals is adapted to receive an input signal, and ... | 06/20/2006 |
