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| Number | Title | Issue Date |
| 8179186 | Differential switch with off-state isolation enhancement Techniques are disclosed for reducing off-state leakage current in a differential switching device. The techniques can be embodied, for example, in a method that includes receiving a differential input signal at a differential input of each of a primary switch and a... | 05/15/2012 |
| 8085080 | Generation of a low jitter clock signal Systems and methods for generation of a low jitter clock signal for wireless circuits are disclosed. In an implementation, the system includes a wireless circuit powered by a first power supply and a low jitter clock (LJC) generator powered by a second power supply.... | 12/27/2011 |
| 7940110 | Cascode switching circuit A switch circuit is disclosed. The switch circuit may include one or more arrangements of transistors coupled in a cascode configuration. The transistors used to implement the switch circuit may be configured for operation within a first range of voltages. The appli... | 05/10/2011 |
| 7920013 | Systems and methods for oscillation suppression in switching circuits A switching circuit configured to reduce the effects of signal oscillation on the operation of the switching circuit is provided. The switching circuit may include signal oscillation and detection circuitry that suppresses control signals during a detected oscillati... | 04/05/2011 |
| 7915944 | Gate drive circuitry for non-isolated gate semiconductor devices One embodiment is a gate drive circuitry for switching a semiconductor device having a non-isolated input, the gate drive circuitry having a first circuitry configured to turn-on the semiconductor device by imposing a current on a gate of the semiconductor device so... | 03/29/2011 |
| 7705655 | Input buffer circuit An input buffer circuit. In one embodiment, the input buffer circuit includes a first transistor operable to receive a first input signal, a second transistor operable to receive a second input signal, and a first mechanism coupled to the first transistor and to the... | 04/27/2010 |
| 7696807 | Semiconductor integrated circuit with input buffer having high voltage protection A high voltage reception terminal is formed in a semiconductor integrated circuit without increasing the number of manufacturing processes and the manufacturing cost. A transfer gate configured from a NMOS, which is the high withstand voltage transistor, and a pull-... | 04/13/2010 |
| 7649400 | Back gate biasing overshoot and undershoot protection circuitry The signal switch has flat resistance across the input/output voltage range when in the ON state while still isolating input/output nodes from overshoots and undershoots when in the off state. The signal switch includes: a p channel switch coupled between a first in... | 01/19/2010 |
| 7576587 | On-chip source termination in communication systems A communication system includes an integrated circuit (IC) die having an on-chip source termination. The on-chip source termination can be a non-precision resistor, such as an unsilicided poly resistor, or any other suitable termination. As compared to an off-chip s... | 08/18/2009 |
| 7463079 | Short circuit protection by gate voltage sensing A protection circuit monitors the gate voltage of an insulated gate bipolar transistor (IGBT) or metal oxide semiconductor field effect transistor (MOSFET) to protect the transistor during a time when it is being turned on. In one embodiment, the circuit monitors a ... | 12/09/2008 |
| 7453310 | Switching circuit having two MOS-FETS A switching circuit of the present invention can be advantageously used in an electronic control unit mounted on an automotive vehicle. The switching circuit is constituted by a pair of P-channel MOS-FETs connected in series between an input terminal and an output t... | 11/18/2008 |
| 7436237 | Distortion reducing semiconductor switch A semiconductor switch includes a first semiconductor circuit having a nonlinear characteristic, and a second semiconductor circuit having a nonlinear characteristic. Each of the first semiconductor circuit and the second semiconductor circuit is configured to at le... | 10/14/2008 |
| 7408426 | Method and device for transmission without crosstalk The invention relates to a method and a device for transmission without crosstalk in interconnections used for sending a plurality of signals, such as the interconnections made with flat multiconductor cables, or with the tracks of a printed circuit board, or inside... | 08/05/2008 |
| 7397292 | Digital input buffer with glitch suppression A delay and deglitching circuit suppresses glitches occurring in a received digital signal while introducing a predetermined delay to the signal. The deglitching circuit comprises an RC filter and a Schmitt trigger. A node at the input of the Schmitt trigger fed by ... | 07/08/2008 |
| 7348809 | Input buffer In one embodiment, the present invention includes an input buffer with a common gate amplifier having input terminals coupled to receive an incoming common mode voltage. The common gate amplifier may be configured to receive the incoming common mode voltage over a w... | 03/25/2008 |
| 7337419 | Crosstalk noise reduction circuit and method In a semiconductor device, a method for reducing the effect of crosstalk from an aggressor line to a victim line begins with sensing the occurrence of a voltage change on the aggressor line that can induce a voltage pulse having a pulse magnitude that exceeds a puls... | 02/26/2008 |
| 7336105 | Dual gate transistor keeper dynamic logic A dynamic logic gate has a device for charging a dynamic node during a pre-charge phase of a clock. A logic tree evaluates the dynamic node with a device during an evaluate phase of the clock. The dynamic node has a keeper circuit comprising an inverter with its inp... | 02/26/2008 |
| 7327130 | Current sense method A current-sense circuit for measuring a load current in a switching power regulator may operate independently of process variation and temperature, and measure bi-directional load currents without requiring high-speed, high-voltage amplifiers for operation. A positi... | 02/05/2008 |
| 7317441 | Constant current circuit, drive circuit and image display device A first amplifier circuit (132) included in a voltage generating circuit (114) includes a differential circuit formed of P-type TFT elements (P101, P102) and N-type TFT elements (N101, N102), a constant current circuit (1... | 01/08/2008 |
| 7312659 | Multi-amplifier circuit An amplifier circuit includes first, second, third and fourth transconductance amplifiers that each have an input, an output and a transconductance gain. The outputs of the first, second and third amplifiers communicate with the inputs of the second, third and fourt... | 12/25/2007 |
| 7304595 | Current output circuit A capacitor having a capacitance value corresponding to the size of an output current generating transistor is connected between the gate terminal of the output current generating transistor and the input terminal of an inverter circuit. ... | 12/04/2007 |
| 7286001 | High-frequency switching device and semiconductor device The first terminals of a plurality of resistor elements are connected to the intermediate connection points of a plurality of FETs connected in series, and a voltage, having a phase opposite to that of the voltage applied to the gate terminals of the plurality of FE... | 10/23/2007 |
| 7276969 | Multi-amplifier circuit A transimpedance amplifier circuit includes a first amplifier with an input, an output and a first transconductance. A second amplifier has an input that communicates with the output of the first amplifier, an output and a second transconductance. A first resistance... | 10/02/2007 |
| 7275004 | Method and apparatus to perform on-die waveform capture An integrated circuit is provided that includes a first port to receive a first signal from a first channel and a first device coupled to the first port to modify a channel response of the first signal received from the first channel. A waveform capture device may b... | 09/25/2007 |
| 7271626 | Suppression of parasitic ringing at the output of a switched capacitor DC/DC converter A multi-stage transistor circuit is provided in which the multiple transistor stages are coupled in parallel and switched individually in sequence by a series arrangement of buffers. Each buffer drives the gate of a corresponding stage of the multi-stage transistor ... | 09/18/2007 |
| 7271627 | High voltage tolerant input buffer operable in under-drive conditions An input buffer includes a signal passing module for generating a first output signal in response to the input signal based on a comparison between the input signal and a first supply voltage thereof; a regulating module having a first input terminal receiving the i... | 09/18/2007 |
| 7268378 | Structure for reduced gate capacitance in a JFET A junction field effect transistor (JFET) with a reduced gate capacitance. A gate definition spacer is formed on the wall of an etched trench to establish the lateral extent of an implanted gate region for a JFET. After implant, the gate is annealed. In addition to ... | 09/11/2007 |
| 7262461 | JFET and MESFET structures for low voltage, high current and high frequency applications JFET and MESFET structures, and processes of making same, for low voltage, high current and high frequency applications. The structures may be used in normally-on (e.g., depletion mode) or normally-off modes. The structures include an oxide layer positioned under th... | 08/28/2007 |
| 7256637 | High voltage switching apparatus A switching arrangement for a high voltage load provides high voltage pulses to the load. The switching arrangement includes switching modules, where n is typically (75). A load capacitance is Cd is required to avoid voltage overshoot at the load and is provi... | 08/14/2007 |
| 7245170 | Attenuator and portable telephone terminal apparatus using the same Provided are: at least one or more series variable resistors implemented by field effect transistors connected to a signal line A; and at least one or more shunt variable resistors implemented by field effect transistors connected between a signal outputting section... | 07/17/2007 |
| 7245173 | Method to reduce integrated circuit power consumption by using differential signaling within the device A method of power consumption reduction in integrated circuits comprising extensive use of differential signaling within said circuits. Differential signaling comprises a pair of coupled, symmetrically opposite and operatively dependent electronic signals each drive... | 07/17/2007 |
| 7242227 | Common mode stabilization circuit for differential bus networks A differential bus network, in general, or a controller area network (CAN) driver, in particular, controls and minimizes the variation on the common-mode signal of the CAN bus. This CAN driver also provides improved symmetry between its differential output signals, ... | 07/10/2007 |
| 7239185 | Driver circuit connected to pulse shaping circuitry An integrated circuit driver includes an output stage having source drain paths of a PFET and NFET connected in series with each other across DC power supply terminals. A pair of inverters simultaneously responsive to a bilevel signal drive gate electrodes of the PF... | 07/03/2007 |
| 7228110 | Low cost high frequency device having compact mounting area, high frequency amplification method, wireless communication device and mobile telephone including low cost and high frequency circuit having compact mounting area A high frequency device includes a transmission/reception amplifier 13 that amplifies and outputs an input signal, and a transmission/reception switch 2 that gang switches internally so that during transmission an input of the transmission/reception am... | 06/05/2007 |
| 7224212 | Low pass filter de-glitch circuit A low pass filter de-glitch circuit is disclosed herein, it includes a first short pulse resetting circuit, a second short pulse resetting circuit having MOS transistors and a low pass filtering circuit having a capacitor coupled with an inverter. Forgoing circuits ... | 05/29/2007 |
| 7212060 | Ground bounce protection circuit for a test mode pin A test-mode circuit allows the same pad of a semiconductor device to be used as a test pad during test operations and as an I/O pad during normal operations. The test-mode circuit is coupled between the pad and a reference signal (Vbg) of the device, and in response... | 05/01/2007 |
| 7212046 | Power-up signal generating apparatus In a power-up signal generating device, a power-up signal is activated at a certain level of the power supply voltage VDD by adjusting the turn-on resistance value of the MOS transistor so that the chip reliability can be improved. The power-up signal generating dev... | 05/01/2007 |
| 7199635 | High-frequency switching device and semiconductor The first terminals of a plurality of resistor elements are connected to the intermediate connection points of a plurality of FETs connected in series, and a voltage, having a phase opposite to that of the voltage applied to the gate terminals of the plurality of FE... | 04/03/2007 |
| 7190195 | Input circuit and output circuit An input circuit is provided which prevents malfunctioning of a function circuit during a power source voltage rise without the need of a separate Under Voltage Lock Out (UVLO) circuit. The input circuit includes a first transistor which receives an input terminal s... | 03/13/2007 |
| 7173475 | Signal transmission amplifier circuit A signal transmission amplifier circuit has a transmission gate with an input coupled to an input signal. A cross coupled latch is coupled to an output of the transmission gate and has a signal output. A reference generating circuit is coupled to the cross coupled l... | 02/06/2007 |
