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| Number | Title | Issue Date |
| 7999599 | Adaptive bias circuit Disclosed are apparatus and methods for electronic signal conversion in which a power level of the signal is used to adjust the bias current of a converter. ... | 08/16/2011 |
| 7382175 | Frequency mixer preventing degradation in linearity on amplitude of input signal A frequency mixer includes a first N channel MOS transistor, second and third N channel MOS transistors constituting a local oscillator signal differential pair, and having substantially identical properties, a first load, and a second load. The first N channel MOS ... | 06/03/2008 |
| 7375577 | Mixer capable of detecting or controlling common mode voltage thereof A mixer capable of detecting or controlling a common mode voltage thereof, includes at least: a mixing module for mixing a first set of differential signals and a second set of differential signals to generate at least one mixed signal; and a compensation module for... | 05/20/2008 |
| 7245164 | Radio frequency doubler When a signal of a double frequency is generated from the original signal, conventionally a 90-degree phase-shift circuit is necessary to suppress an output of a DC component and efficiently obtain a double wave. According to the present invention, an equal RF signa... | 07/17/2007 |
| 7236761 | Balanced circuit arrangement and method for linearizing such an arrangement The present invention relates to a balanced circuit arrangement and methods for linearizing and calibrating such a circuit arrangement, wherein linearization is obtained by introducing a load imbalance between the output branches of the balanced circuit arrangement.... | 06/26/2007 |
| 7218163 | Radio-frequency mixer arrangement The present invention relates to a radio-frequency mixer arrangement in which a differential amplifier is connected to an input on a multiplier. The differential amplifier is arranged together with at least one capacitance in the feedback path of an operational ampl... | 05/15/2007 |
| 7199651 | Frequency selection using capacitance multiplication A variable capacitance circuit on an integrated circuit comprises a MOS transistor, and a capacitance multiplier connected to one end of a channel of the MOS device. A MOS device is formed in series with an inductance, and a capacitance multiplier is formed to be co... | 04/03/2007 |
| 7123073 | Amplifier and frequency converter An amplifier circuit amplifies a differential signal supplied by a pair of input terminals. A phase controller circuit is placed between the emitters of two bipolar transistors and the ground. A feedback circuit is placed across the input and the output of the ampli... | 10/17/2006 |
| 7099646 | Signal mixer having a single-ended input and a differential output A single-ended-to-differential mixer includes a differential input circuit having a single-ended input. The differential input circuit is responsive to a single-ended input signal to generate first and second signals. The single-ended-to-differential mixer includes ... | 08/29/2006 |
| 7054609 | Linearity improvement of Gilbert mixers Method and system are disclosed for providing an improved linearity Gilbert mixer. The Gilbert mixer of the present invention includes a conventional mixer core coupled to a high linearity, multistage amplifier. The multistage amplifier includes two or more transist... | 05/30/2006 |
| 7042200 | Switching mode power conversion with digital compensation The present invention provides improved line and load regulation of a switching-mode power converter (300) without requiring additional capacitors (255), either internally or externally, to stabilize the control loop. The present invention can provide ... | 05/09/2006 |
| 7031687 | Balanced circuit arrangement and method for linearizing such an arrangement The present invention relates to a balanced circuit arrangement and methods for linearizing and calibrating such a circuit arrangement wherein linearization is obtained by introducing a load imbalance between the output branches of the balanced circuit arrangement. ... | 04/18/2006 |
| 6982578 | Digital delay-locked loop circuits with hierarchical delay adjustment Fine tuned signal phase adjustments are provided by multiple cascaded phase mixers. Each phase mixer outputs a signal having a phase between the phases of its two input signals. With each subsequent stage of phase mixers, the signals generated by the phase mixers ha... | 01/03/2006 |
| 6943619 | Practical active capacitor filter A method and apparatus is described that filters an electrical signal. The filtering uses a capacitor multiplier circuit where the capacitor multiplier circuit uses at least one amplifier circuit and at least one capacitor. A filtered electrical signal results from ... | 09/13/2005 |
| 6892061 | Mixer circuit configuration A circuit configuration for mixing a differential desired signal with a differential local oscillator signal includes two difference amplifiers which are controllable on the input side by the desired signal and cross-coupled on the output side. Currents flowing thro... | 05/10/2005 |
| 6642767 | DC offset cancellation DC offset canceling is disclosed. A DC level fixing signal generator receives feedback input of two output signals from a mixer and generates a level fixing control signal to fix the DC level of the two output signals according to the input values. A DC o... | 11/04/2003 |
| 6617910 | Low noise analog multiplier utilizing nonlinear local feedback elements A voltage controlled amplifier is improved in noise performance with nonlinear local feedback elements while maintaining low distortion for various control settings. By paralleling nonlinear elements, distortion is further improved. Preferably, these nonl... | 09/09/2003 |
| 6594478 | Self oscillating mixer A self oscillating mixer circuit includes a dual gate FET, an NDR device coupled to a first gate of the FET, and a first bias input circuit adapted to couple a first bias voltage across the NDR device. The first bias voltage controls operation of the NDR ... | 07/15/2003 |
| 6456142 | Circuit having dual feedback multipliers An analog multiplier circuit utilizes a dual feedback structure, in which two multiplier core sections can be progressively enabled or disabled to varying degrees, thereby providing variable gain while maintaining constant bandwidth. The multipliers are p... | 09/24/2002 |
| 6400936 | Low-noise lossless feedback double-balanced active mixers A low-noise, linearized double-balanced active mixer circuit is described, including a first input for a local oscillator (LO), a second input for an intermediate frequency (IF) signal, and an output for a resulting product radio frequency (RF) signal. Th... | 06/04/2002 |
| 6342804 | Low-noise mixer A four-quadrant mixer is disclosed which has a low noise factor. The indeterminate common-mode voltage that may accompany the modulating signal is suppressed and replaced by a common-mode quiescent voltage designed to establish a predetermined quiescent b... | 01/29/2002 |
| 6218881 | Semiconductor integrated circuit device A semiconductor integrated circuit device has an output circuit formed in a CMOS structure and composed of a P-channel MOS transistor that has its gate connected to an input terminal, has its source connected to a power source line, and has its drain conn... | 04/17/2001 |
| 6138000 | Low voltage temperature and Vcc compensated RF mixer An RF mixer utilizing frequency and bias compensation for improved performance characteristics. The RF mixer receives bias signals that are dependent on VCC levels to internally balance the local oscillation received and mix the perfectly bias ... | 10/24/2000 |
| 6118268 | Thermoelectric measuring device A thermoelectric measurement converter is disclosed, which forms the output signal as the product of the instantaneous values of two input signals; wherein the measurement converter comprises at least one electronic resistor and at least one temperature s... | 09/12/2000 |
| 5910745 | Process parameters and temperature insensitive analog divider/multiplier/ratiometry circuit A CMOS analog divider/multiplier/ratiometry circuit that provides a ratiometric output of two or more inputs, where the output is insensitive to process parameters and temperature variations effecting the circuit. The analog divider/multiplier/ratiometry ... | 06/08/1999 |
| 5834963 | Circuit configuration for parameter adjustment A circuit configuration for parameter adjustment has one or more first analog multipliers which receive an input signals and a control signal which cooresponds to a parameter, and which output output signals. A second multiplier, which is identical to the... | 11/10/1998 |
| 5789962 | Multiplication circuit A multiplication circuit has two capacitive couplings connected first and second inverting amplifiers, respectively. Two steps of multiplication are performed by this circuit. Input is multiplied by a multiplier of a product of multipliers of the successi... | 08/04/1998 |
| 5774010 | MOS four-quadrant multiplier including the voltage-controlled-three-transistor V-I converters A MOS four-quadrant multiplier for outputting a combined differential output current corresponding to the product of first and second differential input voltages has first and second two-quadrant multipliers each having a differential output. Each of the ... | 06/30/1998 |
| 5734283 | Demultiplexor circuit A delay line and clock multiplying circuit are disclosed. A plurality of phase shifters impart on a reference clock successively increasing phase shifters, wherein the phase shifters have a plurality of outputs for the successively phase shifted signals. ... | 03/31/1998 |
| 5708384 | Computational circuit A computational circuit which has a capacitive coupling for weighted addition. Addition is performed by the capacitive coupling. By connecting and disconnecting capacitances of the capacitive coupling, multiplication can be executed by changing the weight... | 01/13/1998 |
| 5680070 | Programmable analog array and method for configuring the same A programmable analog array (10) comprises an array (11) of cells, each cell including analog circuitry (12), a switch control circuit (18), and a digital storage element (16). The switch control circuit (18) receives a clock signal and sequentially confi... | 10/21/1997 |
| 5652537 | Impedance multiplier An impedance multiplier circuit comprises an input impedance having a certain value of impedance and a circuit coupled to this input impedance for multiplying its value by a multiplication factor. This multiplying circuit comprises a first and a second vo... | 07/29/1997 |
| 5627486 | Current mirror circuits and methods with guaranteed off state and amplifier circuits using same Current mirror circuits and methods, and an amplifier using same, are provided in which the output of the current mirror is reduced to zero when the input current falls below a predetermined threshold. An offset current is subtracted from the input (or re... | 05/06/1997 |
| 5606738 | Frequency conversion circuit with linear feedback A frequency conversion circuit having at least one transistor with an input terminal and an output terminal. A frequency signal to be converted or a local oscillator (LO) signal is input to the input terminal, and a converted frequency signal is output fr... | 02/25/1997 |
| 5570056 | Bipolar analog multipliers for low voltage applications An analog circuit for multiplying a first input signal with a second input signal. The inventive analog circuit is capable of linear operation with a low voltage power source. A first pair of transistors is coupled as a first differential pair, and a seco... | 10/29/1996 |
| 5568080 | Computational circuit A computational circuit that includes a selector for providing an input to one of a plurality of sample/hold circuits. The outputs of the sample/hold circuits are provided to a multiplexer. The output of the multiplexer is provided to a computational port... | 10/22/1996 |
| 5565809 | Computational circuit A computational circuit that includes a pair of operational amplifiers, wherein one of the amplifiers receives an analog input voltage. Switching circuits are provided to selectively connect the outputs of the operational amplifiers to a common node and t... | 10/15/1996 |
| 5450029 | Circuit for estimating a peak or RMS value of a sinusoidal voltage waveform An estimating circuit for application in estimating or deriving the value Vrms2 or Vpeak2, of a line voltage VAC provides fast response time and a substantially ripple free value for these signals by ... | 09/12/1995 |
| 5057716 | Linearly compensated slope multiplier An electronic multiplier circuit in which a first differential amplifier is introduced into the negative feedback of an input amplifier, an input of the first differential amplifier is connected to an input of a second differential amplifier and the colle... | 10/15/1991 |
| 4818951 | Gain control or multiplier circuits This invention concerns, in a current-controlled amplifier circuit, the combination of output amplifier means having an input conductor and having an output conductor for converting a signal at the input conductor of the output amplifier means to a curren... | 04/04/1989 |
