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| Number | Title | Issue Date |
| 7420405 | Electronic isolator The present invention is an electronic isolator that provides low input to output insertion loss, high output to input insertion loss, and substantial asymmetric isolation between a source circuit and a load circuit. The invention actively reduces noise and reflecte... | 09/02/2008 |
| 7370134 | System and method for memory hub-based expansion bus A system memory includes a memory hub controller, a memory module accessible by the memory hub controller, and an expansion module having a processor circuit coupled to the memory module and also having access to the memory module. The memory hub controller is coupl... | 05/06/2008 |
| 7366864 | Memory hub architecture having programmable lane widths A processor-based system includes a processor coupled to a system controller through a processor bus. The system controller is used to couple at least one input device, at least one output device, and at least one data storage device to the processor. Also coupled t... | 04/29/2008 |
| 7362157 | Circuit arrangement with a transistor having a reduced reverse current A circuit arrangement is disclosed herein having an input terminal configured to receive an input voltage, and an output terminal to provide an output voltage for a load. A first transistor with a load path and a control terminal is connected between the input termi... | 04/22/2008 |
| 7362292 | Active matrix display device An active matrix display device has column address circuitry for generating pixel drive signals. The column address circuitry has an output buffer for providing a pixel drive signal to a column conductor, and the positive and negative slew rates of the output buffer... | 04/22/2008 |
| 7358771 | System including a single ended switching topology for high-speed bidirectional signaling A system including a single ended switching topology for high-speed bidirectional signaling includes a device coupled to a plurality of bidirectional signal paths. The device includes a plurality of voltage mode driver circuits, each coupled to a respective signal p... | 04/15/2008 |
| 7348809 | Input buffer In one embodiment, the present invention includes an input buffer with a common gate amplifier having input terminals coupled to receive an incoming common mode voltage. The common gate amplifier may be configured to receive the incoming common mode voltage over a w... | 03/25/2008 |
| 7334137 | Memory interface systems that couple a memory to a memory controller and are responsive to a terminal voltage that is independent of supply voltages for the memory and the memory controller Memory interface systems include one or more channel lines that couple a memory to a memory controller such that the channel line(s) are responsive to a terminal voltage that is independent of supply voltages for the memory and the memory controller. Because the mem... | 02/19/2008 |
| 7317346 | Selecting a bias for a level shifting device One or more MOS devices may be used as a bias selecting circuit to pass a bias voltage from a bias generator to a level shifting circuit. ... | 01/08/2008 |
| 7301386 | Apparatus for improved delay voltage level shifting for large voltage differentials A voltage level shifting device for translating a lower operating voltage to a higher operating voltage includes a first input node coupled to a first pull down device and a second input node coupled to a second pull down device. The second node receives a complemen... | 11/27/2007 |
| 7289347 | System and method for optically interconnecting memory devices A memory device includes a semiconductor substrate in which memory circuitry has been fabricated. An address converter and a control signal converter are coupled to an address decoder and control logic, respectively. The address and control converters are operable t... | 10/30/2007 |
| 7285992 | Amplifier with charge-pump generated local supplies An amplifier system includes a follower-type output stage that is driven by a pre-driver circuit. The follower-type output stage that is operated from VCC and GND (or VEE) power supplies. The pre-driver circuit for the follower output stage is operated from local po... | 10/23/2007 |
| 7280419 | Latency counter having frequency detector and latency counting method thereof The present invention discloses a latency counter applied to a memory, for delaying a memory accessing control signal. The latency counter includes: a clock delay module for applying at least one delay amount to the input clock to generate a delayed input clock; a f... | 10/09/2007 |
| 7271635 | Method and apparatus for reducing duty cycle distortion of an output signal A method and apparatus for reducing the duty cycle distortion of a periodic signal in high speed devices. More specifically, there is provided a device having a switching point modulation circuit coupled to input logic and configured to modulate the periodic output ... | 09/18/2007 |
| 7268603 | Method and apparatus for reducing duty cycle distortion of an output signal A method and apparatus for reducing the duty cycle distortion of a periodic signal in high speed devices. More specifically, there is provided a device having a switching point modulation circuit coupled to input logic and configured to modulate the periodic output ... | 09/11/2007 |
| 7266633 | System and method for communicating the synchronization status of memory modules during initialization of the memory modules A memory system includes a memory hub controller coupled to a plurality of memory modules each of which includes a memory hub. The memory hub controller and the memory hubs each include at least one receiver that is synchronized to an internal clock signal during in... | 09/04/2007 |
| 7254331 | System and method for multiple bit optical data transmission in memory systems The disclosed system and method data increases data transmission speed through a memory system by using optical signals comprising a plurality of wavelengths of light so that each pulse of optical signals can represent more than a single bit of data. An optical tran... | 08/07/2007 |
| 7248092 | Clamp circuit device In a clamp circuit device, reference voltages are set up by a series circuit of an FET, a resistor and an FET. Gate potentials of FETs are set up by performing addition and subtraction of these reference voltages and a reference voltage generated by a bandgap refere... | 07/24/2007 |
| 7242213 | Memory module and method having improved signal routing topology A registered memory module includes several memory devices coupled to a register through a plurality of transmission lines forming a symmetrical tree topology. The tree includes several branches each of which includes two transmission lines coupled only at its ends ... | 07/10/2007 |
| 7234070 | System and method for using a learning sequence to establish communications on a high-speed nonsynchronous interface in the absence of clock forwarding A memory system includes a memory hub controller that sends write data to a plurality of memory modules through a downstream data bus and receives read data from the memory modules through an upstream data bus. The memory hub controller includes a receiver coupled t... | 06/19/2007 |
| 7222210 | System and method for memory hub-based expansion bus A system memory includes a memory hub controller, a memory module accessible by the memory hub controller, and an expansion module having a processor circuit coupled to the memory module and also having access to the memory module. The memory hub controller is coupl... | 05/22/2007 |
| 7222213 | System and method for communicating the synchronization status of memory modules during initialization of the memory modules A memory system includes a memory hub controller coupled to a plurality of memory modules each of which includes a memory hub. The memory hub controller and the memory hubs each include at least one receiver that is synchronized to an internal clock signal during in... | 05/22/2007 |
| 7209333 | Apparatus and method for over-voltage, under-voltage and over-current stress protection for transceiver input and output circuitry A circuit for protection of a transceiver input includes an input transistor and a first resistor connected between the drain of the input transistor and an input node. A plurality of reverse-biased diodes connected between a supply voltage and the input node. An ou... | 04/24/2007 |
| 7206887 | System and method for memory hub-based expansion bus A system memory includes a memory hub controller, a memory module accessible by the memory hub controller, and an expansion module having a processor circuit coupled to the memory module and also having access to the memory module. The memory hub controller is coupl... | 04/17/2007 |
| 7200024 | System and method for optically interconnecting memory devices A memory device includes a semiconductor substrate in which memory circuitry has been fabricated. An address converter and a control signal converter are coupled to an address decoder and control logic, respectively. The address and control converters are operable t... | 04/03/2007 |
| 7180797 | Reduced power registered memory module and method A registered memory module includes a plurality of flip-flops having respective data terminals, respective clock terminals receiving a clock signal and output terminals coupled to a plurality of SDRAM devices in the module. A logic gate decodes respective chip selec... | 02/20/2007 |
| 7180354 | Receiver having full signal path differential offset cancellation capabilities There is described an improved receiver which first comprises an analog input amplifier a sample and hold differential circuit and two stages of differential comparators that are connected in series, wherein the first stage consists of two comparators and the second... | 02/20/2007 |
| 7181584 | Dynamic command and/or address mirroring system and method for memory modules A memory module includes a memory hub that couples signals to memory devices mounted on opposite first and second surfaces of a memory module substrate. The memory devices are mounted in mirrored configuration with mirrored terminals of memory devices on opposite su... | 02/20/2007 |
| 7174470 | Computer data bus interface control A computer data bus interface control selectively connects a computer data bus to functional components of a circuit board or isolates the bus from the functional components. The bus interface control also selectively provides pull-up voltage to the bus, as needed. ... | 02/06/2007 |
| 7174409 | System and method for memory hub-based expansion bus A system memory includes a memory hub controller, a memory module accessible by the memory hub controller, and an expansion module having a processor circuit coupled to the memory module and also having access to the memory module. The memory hub controller is coupl... | 02/06/2007 |
| 7159067 | Information processing apparatus using index and TAG addresses for cache In an information processing apparatus involving a cache accessed by INDEX and TAG addresses, accesses to the main memory include many accesses attributable to the local character of referencing and write-back accesses attributable to the replacement of cache conten... | 01/02/2007 |
| 7137024 | System and method for using a learning sequence to establish communications on a high-speed nonsynchronous interface in the absence of clock forwarding A memory system includes a memory hub controller that sends write data to a plurality of memory modules through a downstream data bus and receives read data from the memory modules through an upstream data bus. The memory hub controller includes a receiver coupled t... | 11/14/2006 |
| 7123059 | Output stage resistant against high voltage swings Circuit comprising a signal input (11) for receiving an input signal (s(t)) and a digital output stage (15) being designed for operation at a supply voltage (VDD). The output stage (15) comprises a series of two n-channel CMOS transis... | 10/17/2006 |
| 7123522 | Method and apparatus for achieving low power consumption during power down The present technique relates to a method and apparatus to provide a deep power down mode. In a memory device, such as DRAM or SRAM, various internal voltage buses provide power throughout the semiconductor chip. In a deep power down mode, grounding devices may be u... | 10/17/2006 |
| 7120723 | System and method for memory hub-based expansion bus A system memory includes a memory hub controller, a memory module accessible by the memory hub controller, and an expansion module having a processor circuit coupled to the memory module and also having access to the memory module. The memory hub controller is coupl... | 10/10/2006 |
| 7106611 | Wavelength division multiplexed memory module, memory system and method A computer system includes a controller linked to a plurality of memory modules each of which has an optical memory hub and several memory devices coupled to the memory hub. The controller communicates with the memory hubs by coupling optical signals to and from the... | 09/12/2006 |
| 7091744 | Input termination circuits and methods for terminating inputs An input signal provided to an input terminal is terminated by coupling the input terminal to a ground voltage through a pull down transistor if the input signal at the input terminal is at a “high” level and coupling the input terminal to a power voltage throug... | 08/15/2006 |
| 7079439 | Low power auto-refresh circuit and method for dynamic random access memories A power saving circuit disables input buffers for command and address signals during an auto-refresh of a DRAM. The input buffers are re-enabled at the end of the auto-refresh in a manner that does not cause spurious commands to be generated. The power saving circui... | 07/18/2006 |
| 7072231 | Reduced power registered memory module and method A registered memory module includes a plurality of flip-flops having respective data terminals, respective clock terminals receiving a clock signal and output terminals coupled to a plurality of SDRAM devices in the module. A logic gate decodes respective chip selec... | 07/04/2006 |
| 7034565 | On-die termination circuit and method for reducing on-chip DC current, and memory system including memory device having the same Provided are an on-die termination (“ODT”) circuit and ODT method which are capable of minimizing consumption of an on-chip DC current, and a memory system which adopts a memory device having the same, where the ODT circuit includes a termination voltage port, a... | 04/25/2006 |
