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| Number | Title | Issue Date |
| 7443703 | Semiconductor device A semiconductor device has a semiconductor element connected to an input/output terminal and a reference voltage terminal, a first rectifier element connected between the input/output terminal and the reference voltage terminal, which performs rectifier operation to... | 10/28/2008 |
| 7372681 | Electrostatic discharge (ESD) protection device with simultaneous and distributed self-biasing for multi-finger turn-on An electrostatic discharge (ESD) protection circuit for a semiconductor integrated circuit (IC) that protects core circuitry of the IC during normal operations, and shunts ESD events during non-powered mode of the IC. The ESD protection circuitry includes a multi-fi... | 05/13/2008 |
| 7355466 | Passive mixer with direct current bias Mixer circuits with direct-current bias are disclosed. An example embodiment of such a mixer includes a first differential transistor pair and a second differential transistor pair. The example mixer also includes first and second local oscillator signal terminals a... | 04/08/2008 |
| 7336459 | Electrostatic discharge protection device and circuit thereof An electrostatic discharge (ESD) protection circuit including a detection circuit for detecting the ESD current and a clamp circuit for bypassing an ESD current between a first pad and a second pad is provided. The detection circuit is connected between the first pa... | 02/26/2008 |
| 7298213 | Input impedance matching circuit for low noise amplifier An input impedance matching circuit for a low noise amplifier includes a source pad, a gate pad, an input transistor, a source degeneration inductor and a matching capacitor. The gate pad receives an input signal and the input transistor amplifies the input signal t... | 11/20/2007 |
| 7239077 | Display device For absorbing a high voltage when an abnormal discharge is generated between an anode and another electrode, between an anode ADE and a control electrode G1, a surge current absorbing electrode G2 which has a plurality of electron beam passing holes AH... | 07/03/2007 |
| 7215005 | Bipolar ESD protection structure The invention describes the fabrication and structure of an ESD protection device for integrated circuit semiconductor devices with improved ESD protection and resiliency. A vertical bipolar npn transistor forms the basis of the protection device. To handle the larg... | 05/08/2007 |
| 7170269 | Low dropout regulator with control loop for avoiding hard saturation A hard saturation mode of operation can be avoided in an LDO regulator by providing an additional feedback control loop. The additional control loop cooperates with the LDO regulator's amplifier stage and output stage to maintain at least a minimum desired voltage d... | 01/30/2007 |
| 7139990 | Method of checking the layout versus the schematic of multi-fingered MOS transistor layouts using a sub-circuit based extraction A sub-circuit based extraction method which extracts a multi-finger MOS transistor directly as a sub-circuit is described. By adding three marking layers, the method provides the layout extracted netlist with a complete list of device geometric parameters correspond... | 11/21/2006 |
| 7129759 | Integrated circuit including an overvoltage protection circuit The power IC includes an output transistor M0 which controls a current flowing into an L load, a dynamic clamp circuit which clamps an overvoltage, and a clamp control circuit which controls the operation of the dynamic clamp circuit. The clamp control circui... | 10/31/2006 |
| 7108711 | Protection apparatus for implantable medical device A method and apparatus for protecting an electronic implantable medical device prior to it being implanted in a patient's body. The apparatus affords protection against electronic component damage due to electrostatic discharge and/or physical damage due to improper... | 09/19/2006 |
| 7068090 | Amplifier circuit An amplifier circuit includes a CMOS inverter circuit that eliminates a DC offset caused by variations in characteristics of elements in each manufacturing process and is thus applicable to analog signal processing. The CMOS inverter circuit includes a PMOS transist... | 06/27/2006 |
| 7030677 | Frequency compensation scheme for low drop out voltage regulators using adaptive bias A method and circuits to improve the stability of low dropout voltage regulators having an adaptive biased driving stage. Said improvement of stabilization is valid through the total range of output current possible. A serial impedance is added to the gate capacitan... | 04/18/2006 |
| 7002221 | Bipolar transistor having raised extrinsic base with selectable self-alignment and methods of forming same A bipolar transistor with raised extrinsic base and selectable self-alignment between the extrinsic base and the emitter is disclosed. The fabrication method may include the formation of a predefined thickness of a first extrinsic base layer of polysilicon or silico... | 02/21/2006 |
| 6963214 | OBIRCH dual power circuit Methods and apparatus for testing a semiconductor structure requiring a precise core or operating voltage with an OBIRCH analysis arrangement. The separate power supply used for providing the precise core or operating voltage is eliminated, and is replaced by connec... | 11/08/2005 |
| 6947337 | Random-access memory devices comprising a dioded buffer Random-access memory device having select lines, bit lines, and several RAM cells, each RAM cell being connected to a corresponding one of said select lines and to a corresponding one of said bit lines. The random-access memory device further having select buffers f... | 09/20/2005 |
| 6946865 | Semiconductor integrated circuit apparatus A semiconductor integrated circuit apparatus includes a first controlled circuit halving at least one MOS transistor and a substrate bias control unit for generating a substrate bias voltage of the MOS transistor, wherein when the substrate bias control unit is set ... | 09/20/2005 |
| 6927996 | Magnetic memory device A magnetic random access memory (MRAM) includes an array of magnetic memory cells arranged on a cross-point grid. Spurious voltages that build up on the stray wiring capacitance of unselected bit and word select lines are limited and discharged by diodes. The contro... | 08/09/2005 |
| 6894567 | ESD protection circuit for use in RF CMOS IC design An improved method is presented for adding ESD protection to large signal MOS circuits. Each of the ESD and the MOS devices are separately connected off chip to rigid voltage points, thereby eliminating additional capacitive loading of MOS devices. An improve... | 05/17/2005 |
| 6847248 | Sub-micron high input voltage tolerant input output (I/O) circuit which accommodates large power supply variations A method of providing bias voltages for input output connections on low voltage integrated circuits. As integrated circuit voltages drop generally so does the external voltages that those circuits can handle. By placing input and output devices, in series, external ... | 01/25/2005 |
| 6777996 | Radio frequency clamping circuit A clamping circuit (10) including an input/output node (12), adapted to be coupled to the protected circuit or component; a first diode (D1) having an anode connected to the input/output node (12); a second diode (D2) having a cath... | 08/17/2004 |
| 6636118 | High-frequency power amplification module and radio communication device In a high frequency power amplifier module of a multi-stage structure in which a plurality of heterojunction bipolar transistors (npn-type HBTs) are cascade-connected, a protection circuit in which a plurality of pn junction diodes are connected in series... | 10/21/2003 |
| 6529059 | Output stage ESD protection for an integrated circuit An integrated circuit including a transistor having a first electrode coupled to an output bond pad and a second electrode coupled to a reference potential, such as ground bond pad. A degeneration device is coupled between the second electrode and the ref... | 03/04/2003 |
| 6518815 | Power device with protection against undesirable self-activation A MOS-type power device having a drain terminal, a source terminal, and a gate terminal; and a protection circuit having a first conduction terminal connected to the gate terminal, via a diffused resistor, and a second conduction terminal connected to the... | 02/11/2003 |
| 6501319 | Semiconductor device with signal transfer line A noise limiter of a semiconductor integrated circuit device includes a diode-connected N channel MOS transistor between a bus line and a line of a potential lower than the power supply potential by a threshold voltage, and a diode-connected P channel MOS... | 12/31/2002 |
| 6483365 | Semiconductor device A semiconductor device is provided with a signal terminal, a high potential side power supply terminal, a low potential side power supply terminal, a first wiring connected to the high potential side power supply terminal, a second wiring connected to the... | 11/19/2002 |
| 6462601 | Electrostatic discharge protection circuit layout An ESD protection circuit layout. The ESD protection circuit layout has a first ESD protection device, a second ESD protection device, a first CDM ESD protection device, a second CDM ESD protection device, a first charge flow prevention device, a PMOS tra... | 10/08/2002 |
| 6437626 | Device for removing noise in AC power waveform A "PN junction element ta which produces the Peltier effect and Seebeck effect within the same element and imparts a noise reducing effect," which prevents an adverse influence of white noise included in an AC waveform to be supplied from a commercially a... | 08/20/2002 |
| 6414532 | Gate ground circuit approach for I/O ESD protection An I/O ESD protection circuit is provided utilizing a driver circuit, an ESD protection circuit, a Vcc/Vss protection circuit, and a clamping circuit. The driver circuit and the ESD protection circuit each comprise a NMOS cascode circuit. NMOS transistors... | 07/02/2002 |
| 6404261 | Switch circuit and semiconductor switch, for battery-powered equipment A switch circuit for battery-powered equipment, for example a mobile telephone or a portable computer, comprises a 4-terminal bi-directional semiconductor switch (M1) and a protection diode (Dbg). The switch (M1) has a control-gate terminal (g) for applyi... | 06/11/2002 |
| 6404574 | Write driver with diodes to improve switching rate and reliability A write driver, having a pair of head nodes for connection to a write head, includes two diodes connected, respectively to the head nodes and the emitters of first and second upper drive transistors. The diodes increase the voltage necessary to breakdown ... | 06/11/2002 |
| 6400204 | Input stage ESD protection for an integrated circuit An integrated circuit is disclosed in which a steering diode is coupled between an input bond pad and a ground bond pad. The steering diode is reverse biased when a voltage applied to the input bond pad exceeds the voltage at the ground bond pad. A circui... | 06/04/2002 |
| 6396331 | Mechanism for minimizing undesirable effects of parasitic components in integrated circuits A compensation circuit for minimizing undesirable effects of parasitic components, such as a parasitic capacitance of a controlled electronic device (e.g., transistor) is coupled in parallel with the controlled electronic device in a manner that is effect... | 05/28/2002 |
| 6388516 | Precision high speed magnetic coil driver circuit Accuracy of correction of offset drift with temperature and noise are corrected in a high voltage, high current amplifier is improved by thermal isolation and/or temperature regulation of another amplifier having greater gain and connected to a different ... | 05/14/2002 |
| 6388496 | Semiconductor output circuit The present invention relates to a semiconductor output circuit that protects a circuit including such a reverse operation as reverses the potentials of a collector and an emitter of a bipolar transistor. A cathode of a protective diode is connected to a ... | 05/14/2002 |
| 6377120 | Regulated-cascode amplifier with clamping circuit A regulated-cascode amplifier circuit comprising a positive sub-line, a negative sub-line, a first auxiliary amplifier, a second auxiliary amplifier and a clamping circuit. The positive sub-line has a positive output terminal and the negative sub-line has... | 04/23/2002 |
| 6359490 | Clamping circuit and interface circuit therefor The purpose of the present invention is to provide a clamping circuit which has a simple circuit design, with which the clamping voltage range can be easily adjusted, and which can operate at reduced power consumption, as well as interface circuit that ma... | 03/19/2002 |
| 6339356 | Variable attenuator A variable attenuator formed from a combination of PIN diodes is provided. The PIN diodes may be coupled in a "T," "p" or other appropriate configuration. At radio frequencies (RF), a PIN diode acts as a variable resistor with a resistance value based on ... | 01/15/2002 |
| 6333661 | Insulated-gate transistor signal input device An insulated-gate transistor signal input device includes an insulating substrate, a first clock line formed on the insulating substrate to receive a clock signal externally supplied, a clock buffer formed on the insulating substrate to process the clock ... | 12/25/2001 |
| 6288590 | High voltage protection input buffer The present invention provides an improved high voltage protection integrated circuit (IC) input buffer. An IC includes a number of circuit elements and an input pin. Each of the circuit elements can tolerate a process dependent maximum voltage magnitude.... | 09/11/2001 |
