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System for magnetically attaching templeless eyewear to a person
A system of eyewear that eliminates the need for hinges on the frames of the eyewear.
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| Number | Title | Issue Date |
| 8159278 | Method for clamping a semiconductor region at or near ground A clamping circuit clamps a voltage received by an n-type semiconductor region without using a Schottky transistor. The clamping circuit includes a current mirror as well as first and second bipolar transistors. The current mirror receives a first current and suppli... | 04/17/2012 |
| 7999597 | Circuit adjustable after packaging having a voltage limiter and method of adjusting same A circuit adjustable after packaging includes a functional circuit supplied with a power potential and a reference potential and has at least one parameter adjustable by programming at least one programmable element and a circuit to program the programmable element ... | 08/16/2011 |
| 7982523 | Electro static discharge clamping device Electrostatic discharge clamp devices are described. In one embodiment, the semiconductor device includes a first transistor, the first transistor including a first source/drain and a second source/drain, the first source/drain coupled to a first potential node, the... | 07/19/2011 |
| 7800425 | On-chip mode-setting circuit and method for a chip An on-chip mode-setting circuit and method are provided for a chip having an output driver with an output terminal connected to a pin of the chip. The pin may be defined between two states from exterior of the chip. The on-chip mode-setting circuit includes an elect... | 09/21/2010 |
| 7589577 | Circuit adjustable after packaging having a voltage limiter and method of adjusting same A circuit adjustable after packaging includes a functional circuit supplied with a power potential and a reference potential and has at least one parameter adjustable by programming at least one programmable element and a circuit to program the programmable element ... | 09/15/2009 |
| 7372681 | Electrostatic discharge (ESD) protection device with simultaneous and distributed self-biasing for multi-finger turn-on An electrostatic discharge (ESD) protection circuit for a semiconductor integrated circuit (IC) that protects core circuitry of the IC during normal operations, and shunts ESD events during non-powered mode of the IC. The ESD protection circuitry includes a multi-fi... | 05/13/2008 |
| 7372086 | Semiconductor device including MOSFET and isolation region for isolating the MOSFET A semiconductor device comprises a semiconductor substrate, a MOSFET including a double gate structure provided on the semiconductor substrate, and an isolation region for isolating the MOSFET from other elements comprising a trench provided on the surface of the se... | 05/13/2008 |
| 7372301 | Bus switch circuit and interactive level shifter A bus switch circuit includes a switch element having two terminals whose electrical connection is controlled when a control signal is input into a control terminal. The bus switch circuit further includes a first pull-up resistor and first switch circuit, a second ... | 05/13/2008 |
| 7362126 | Floating CMOS input circuit that does not draw DC current A floating CMOS input circuit is disclosed that does not draw direct current. The floating CMOS input circuit comprises a first inverter circuit that is capable of being coupled to an input voltage (Vin) and an n-channel pull-down transistor (N1) that is coup... | 04/22/2008 |
| 7362554 | Electrostatic discharge (ESD) clamp using output driver Electrostatic discharge (ESD) clamp using output driver. An electrostatic discharge (ESD) protection device for an output driver having a p-channel transistor and n-transistor pair connected between a power supply terminal and ground for driving an input/output pad ... | 04/22/2008 |
| 7358788 | Compound semiconductor switching circuit device Protecting elements are respectively connected between a control terminal Ctl and a ground terminal GND of a logic circuit L, between a point Cp and a ground terminal GND, and between a power supply terminal VDD and a ground terminal GND thereof. With thi... | 04/15/2008 |
| 7352032 | Output driver with split pins The drains of the PMOS transistor and the NMOS transistor of a driver are separated and connected to two spaced-apart pins. The spaced-apart pins provide ESD protection to the NMOS transistor, which can be turned on during an ESD event by voltages that propagate thr... | 04/01/2008 |
| 7348641 | Structure and method of making double-gated self-aligned finFET having gates of different lengths A gated semiconductor device is provided, in which the body has a first dimension extending in a lateral direction parallel to a major surface of a substrate, and second dimension extending in a direction at least substantially vertical and at least substantially pe... | 03/25/2008 |
| 7332954 | Eased gate voltage restriction via body-bias voltage governor An arrangement, to ease restriction upon gate voltage (Vgg) magnitudes for a dynamic threshold MOS (DTMOS) transistor, may include: an MOS transistor including a gate and a body; and a body-bias-voltage (Vbb) governor (Vbb-governor) circuit to provide a governed ver... | 02/19/2008 |
| 7286332 | Apparatus for protecting bicycle electrical components An electrical control apparatus comprises a current sensor and a current inhibiting circuit that inhibits current flow between first and second terminals of a bicycle dynamo when current sensed by the current sensor is below a selected value. ... | 10/23/2007 |
| 7279753 | Floating base bipolar ESD devices The present invention includes a bipolar ESD device for protecting an integrated circuit from ESD damage. The bipolar ESD device includes a collector connected to a terminal of the integrated circuit, a floating base, and a grounded emitter. When an ESD pulse hits t... | 10/09/2007 |
| 7271989 | Electrostatic discharge protection circuit Integrated circuits are provided that have sensitive circuitry such as programmable polysilicon fuses. Electrostatic discharge (ESD) protection circuitry is provided that prevents damage or undesired programming of the sensitive circuitry in the presence of an elect... | 09/18/2007 |
| 7256460 | Body-biased pMOS protection against electrostatic discharge A protection circuit for protecting an integrated circuit pad 201 against an ESD pulse, which comprises a discharge circuit having an elongated MOS transistor 202 (preferably pMOS) in a substrate 205 (preferably n-type), said discharge circuit o... | 08/14/2007 |
| 7253033 | Method of manufacturing a semiconductor device that includes implanting in multiple directions a high concentration region In a complete depletion type SOI transistor, the roll-off of a threshold value is suppressed, independently from the formation of an SOI film to be thinner. As for a semiconductor device (1), the impurity concentration in a channel formation portion (10 | 08/07/2007 |
| 7248092 | Clamp circuit device In a clamp circuit device, reference voltages are set up by a series circuit of an FET, a resistor and an FET. Gate potentials of FETs are set up by performing addition and subtraction of these reference voltages and a reference voltage generated by a bandgap refere... | 07/24/2007 |
| 7245171 | Voltage clamping circuit for a bicycle dynamo A voltage clamping circuit comprises a first high current gain circuit adapted to receive current from the first line; and a first switching circuit that turns on the first high current gain circuit to flow current away from the first line when the first switching c... | 07/17/2007 |
| 7242558 | ESD protection module triggered by BJT punch-through An electrostatic discharge protection (ESD) circuit is disclosed for protecting a pad of an integrated circuit from ESD events. The ESD circuit has an ESD trigger module having a first and second transistors connected in series, between the pad and a first common no... | 07/10/2007 |
| 7242226 | Method and apparatus for avoiding false switching in an electronic device A system and method for reducing forward inadvertent biasing of a switch having a transistor. The gate of the transistor is connected to ground and a voltage source less than ground. A control signal of the gate is then applied to a level translator to compensate fo... | 07/10/2007 |
| 7221551 | Cascaded gate-driven ESD clamp A method is provided for semiconductor ESD protection in a mixed voltage device using a cascaded gate driven NMOS clamp circuit. Use of a bias circuit allows for an external I/O signal to have a voltage higher than the internal circuit power supply voltage so that a... | 05/22/2007 |
| 7215142 | Multi-stage inverse toggle An inverse toggle circuit includes a pair of input connections for receiving each of four possible input signal combinations in a sequential rotational manner. Each of four data paths are defined to be exercised in accordance with a respective input signal combinati... | 05/08/2007 |
| 7212058 | Method and apparatus for robust mode selection with low power consumption A low power method and apparatus for selecting operational modes of a circuit. One circuit according to the teachings of the disclosed method and apparatus includes a first current limiting circuit coupled between a selector terminal and a first voltage bus. The fir... | 05/01/2007 |
| 7199636 | Active diode An active diode including a NMOS transistor having a source terminal, a drain terminal, a gate terminal and a back gate terminal, where the source terminal is connected to the back gate terminal and forms the anode terminal of the active diode, and the drain termina... | 04/03/2007 |
| 7170726 | Uniform turn-on design on multiple-finger MOSFET for ESD protection application An electrostatic discharge protection circuit. The electrostatic discharge (ESD) circuit utilizes inductors and resistors added to sources of multiple fingers of the NMOS transistor, which is triggered by some feedback circuit uniformly. When under an ESD zapping, a... | 01/30/2007 |
| 7170772 | Apparatus and method for dynamic control of double gate devices An apparatus for implementing dynamic control of a double gate semiconductor device includes a first switch configured to selectively couple a first gate input of the double gate device to a second gate input of the double gate device, and a second switch configured... | 01/30/2007 |
| 7167042 | Semiconductor device having logic circuit and macro circuit A semiconductor device includes both a logic circuit and a macro circuit. The macro circuit includes a circuit that consumes direct current (DC). In order to conserve power and allow for testing, the consumption of DC by the current consumption circuit can be stoppe... | 01/23/2007 |
| 7154721 | Electrostatic discharge input protection circuit An ESD protection circuit includes: a first metal oxide semiconductor (MOS) transistor discharging an excessive electrostatic current generated between an input pad and an internal circuit, and having a first terminal connected to a ground voltage supply terminal; a... | 12/26/2006 |
| 7148526 | Germanium MOSFET devices and methods for making same A double gate germanium metal-oxide semiconductor field-effect transistor (MOSFET) includes a germanium fin, a first gate formed adjacent a first side of the germanium fin, and a second gate formed adjacent a second side of the germanium fin opposite the first side.... | 12/12/2006 |
| 7138847 | Sub-micron high input voltage tolerant input output (I/O) circuit which accommodates large power supply variations A method of providing bias voltages for input output connections on low voltage integrated circuits. As integrated circuit voltages drop generally so does the external voltages that those circuits can handle. By placing input and output devices, in series, external ... | 11/21/2006 |
| 7135908 | Input stage resistant against high voltage swings An input stage includes a signal input (IN) for receiving an input signal s(t) and a digital input stage (15) designed for operation at a supply voltage (VDD). The input stage (15) includes CMOS transistors, which are sensitive to voltages across trans... | 11/14/2006 |
| 7106563 | Electrostatic discharge protection circuit coupled on I/O pad An I/O pad ESD protection circuit is composed of a SCR circuit, a first diode, a second diode, and an anti-latch-up circuit. The SCR circuit has a first connection terminal and a second connection terminal, respectively coupled to the I/O pad and the ground voltage,... | 09/12/2006 |
| 7098717 | Gate triggered ESD clamp The clamp circuit of the present invention comprises a low voltage, thin oxide MOS transistor and a trigger element comprising a timing element and at least one inverter. The source and drain of the MOS transistor are connected between a first node and a second node... | 08/29/2006 |
| 7098724 | Forward biasing protection circuit A forward biasing protection circuit is provided. More specifically, there is provided a device comprising a transistor, a resistive element coupled to the body terminal of the transistor, and a clamping element coupled in parallel to the resistive element and confi... | 08/29/2006 |
| 7091566 | Dual gate FinFet A field effect transistor (FET), integrated circuit (IC) chip including the FETs and a method of forming the FETS. Each FET includes a device gate along one side of a semiconductor (e.g., silicon) fin and a back bias gate along an opposite of the fin. Back bias gate... | 08/15/2006 |
| 7085872 | High frequency bus system A high frequency bus system which insures uniform arrival times of high-fidelity signals to the devices on the high frequency bus, despite the use of the bus on modules and connectors. A high frequency bus system includes a first bus segment having one or more devic... | 08/01/2006 |
| 7084451 | Circuits with a trench capacitor having micro-roughened semiconductor surfaces A method for forming a trench capacitor. The method includes forming a trench in a semiconductor substrate. A conformal layer of semiconductor material is deposited in the trench. The surface of the conformal layer of semiconductor material is roughened. An insulato... | 08/01/2006 |
