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| Number | Title | Issue Date |
| 8138799 | Inter-phase skew detection circuit for multi-phase clock, inter-phase skew adjustment circuit, and semiconductor integrated circuit An inter-phase skew detection circuit includes a frequency division circuit that frequency-divides N-phase clocks to be measured at predetermined timings so as to generate N+2 frequency-divided clocks; a phase comparison target clock generation circuit that generate... | 03/20/2012 |
| 8138798 | Symmetric phase detector In one embodiment, a circuit includes a first circuit input for receiving a first input signal having a first phase; a second circuit input for receiving a second input signal having a second phase; a circuit output for outputting a circuit output signal; a first mi... | 03/20/2012 |
| 8081013 | Digital phase and frequency detector A method for digital phase detection, comprises the steps of: providing a reference clock; receiving a feedback clock; determining a timing difference between the reference clock and the feedback clock; determining a polarity that indicates the leading or lagging re... | 12/20/2011 |
| 8013636 | Synchronous phase detection circuit A phase detection circuit determines phase difference between a periodic signal and a reference signal of substantially equal frequency. The circuit includes: a source input receiving the periodic signal; a feedback signal generator providing a feedback signal (PFB)... | 09/06/2011 |
| 8008946 | Semiconductor integrated circuit A first counter detects a rising edge of a clock signal, and generates a first signal having a multiplied cycle of the clock signal. A second counter detects a falling edge of the clock signal, and generates a second signal having a multiplied cycle of the cl... | 08/30/2011 |
| 7969202 | Fractional-N frequency synthesizer A circuit, with applications to phase-locked loops and frequency synthesis, where a divider circuit shuffles between dividing the output of a voltage-controlled oscillator by N or N+1, where N is an integer, and where a phase frequency detector provides three logic ... | 06/28/2011 |
| 7839177 | Techniques for phase detection with fast reset A phase detector includes transistors that generate first and second phase error signals. The phase detector resets the first phase error signal in response to at least one of the first and the second phase error signals through a first reset path having a maximum r... | 11/23/2010 |
| 7834664 | Semiconductor device for detecting a phase of a clock A semiconductor, which includes a first phase detecting unit configured to detect a phase of a second clock on the basis of a phase of a first clock, and generate a first detection signal corresponding to a result of the detection, a second phase detecting unit conf... | 11/16/2010 |
| 7812644 | Digital frequency detector and digital phase locked loop using the digital frequency detector A digital frequency detector and a digital phase locked loop (PLL) are provided. The digital frequency detector includes a first conversion unit which outputs a first frequency as first frequency information of a digital type using a first ring oscillator that opera... | 10/12/2010 |
| 7795925 | Phase difference detector and phase difference detection method A phase difference detector for detecting a phase difference between input clocks which both have a same first frequency, including: a pulse width conversion unit for converting the input clocks into a phase difference signal indicating by a pulse width a phase diff... | 09/14/2010 |
| 7777528 | Phase detection module and phase detection method A phase detection module includes a phase detection unit, a plurality of comparators and a decision unit. The phase detection unit is utilized for comparing a first input signal and a second signal to generate a phase detection result. The plurality of comparators i... | 08/17/2010 |
| 7675328 | Phase detection apparatus and phase synchronization apparatus A feedback circuit includes a third variable delay device that controls the amount of phase delay of a first clock; a third logic gate that detects a phase difference between the first clock delayed by the third variable delay device and the first clock, and outputs... | 03/09/2010 |
| 7639048 | System and method of detecting a phase, a frequency and an arrival-time difference between signals A system and method for detecting a phase and a frequency and an arrival-time difference between two signals (118 and 120) that minimizes delay and jitter, and has stable operation even when the two signals (118 and 120) are essentially i... | 12/29/2009 |
| 7622959 | Phase comparator and semiconductor device with phase comparator It is an object of the present invention to improve the phase difference detection accuracy of a phase comparator. A phase difference signal generation circuit outputs a signal C_SIGNAL which takes a high level for a period corresponding to the phase difference betw... | 11/24/2009 |
| 7482841 | Differential bang-bang phase detector (BBPD) with latency reduction Bang-bang phase detection (BBPD) methods and circuits are presented for providing low latency, low jitter phase detection for use in high data-rate applications. A shortened data-path implementation of BBPD methods and circuits provides low-latency production of two... | 01/27/2009 |
| 7456661 | Phase-locked/frequency-locked loop and phase/frequency comparator therefor A phase/frequency comparator is described which includes two edge-triggered storage elements, each set by an edge of a reference frequency signal of a phase—or frequency-locked loop (PLL) and by an edge of an output frequency signal of the PLL. The storage element... | 11/25/2008 |
| 7443251 | Digital phase and frequency detector Disclosed are a digital phase-frequency detector and a method of operating a digital phase-frequency detector. The detector includes an input circuit, an output circuit and a reset circuit. In use, the input circuit receives first and second input signals during a p... | 10/28/2008 |
| 7423456 | Fast response time, low power phase detector circuits, devices and systems incorporating the same, and associated methods A circuit for quickly accomplishing highly accurate phase detection using low power is described. The circuit includes a phase decision circuit that receives two clock signals and detects the phase relationship between the two signals by determining which signal was... | 09/09/2008 |
| 7418071 | Method and apparatus for generating a phase dependent control signal A phase detector generates a phase dependent control signal according to the phase relationship between a first and second clock signal. The phase detector includes first and second phase detector circuits receiving the first and second clock signals and generating ... | 08/26/2008 |
| 7411426 | Phase detector for RZ A phase detector is adapted to receive first and second signals and generate third and fourth signals representative of the difference between the phases of the first and second signals. The phase detector assert the third signal in response to the assertion of the ... | 08/12/2008 |
| 7388408 | Phase-frequency detector capable of reducing dead zone A phase-frequency detector generates output signals at a first and a second output end based on input signals received at a first and a second input end. The phase-frequency detector includes two latch circuits, two pulse generators, two inverting circuits, two sens... | 06/17/2008 |
| 7375557 | Phase-locked loop and method thereof and a phase-frequency detector and method thereof The phase-frequency detector may include a first flip-flop configured to generate a first signal, the first signal transitioning to a first logic level in response to a first edge of a first input signal and transitioning to a second logic level in response to a del... | 05/20/2008 |
| 7373575 | Method and apparatus for generating expect data from a captured bit pattern, and memory device using same Expect data signals are generated for a series of applied data signals having a known sequence to determine if groups of the data signals were properly captured. A first group of the applied data signals is captured, and a group of expect data signals are generated ... | 05/13/2008 |
| 7368954 | Phase comparison circuit and CDR circuit Providing a CDR circuit having a stable clock extracting function and a data regenerating function with a high-speed data input process by reducing the operation speed of the phase comparator circuit. With a phase comparator circuit capable of operating with a clock... | 05/06/2008 |
| 7368963 | Delay locked loop for use in semiconductor memory device and method thereof A delay locked loop (DLL) for generating a delay locked clock signal includes a delay line unit for delaying an external clock signal according to a delay amount control signal to thereby generate the delay locked clock signal; a divider for dividing the delay locke... | 05/06/2008 |
| 7369837 | Frequency-mixing method and frequency-mixing device using the same A frequency-mixing method includes a step of generating a first quadrature signal having a predetermined frequency, a second quadrature signal having a phase difference of about 180 degrees with respect to a phase of the first quadrature signal, a third quadrature s... | 05/06/2008 |
| 7365612 | Low noise, hybrid tuned wideband voltage controlled oscillator An oscillator comprising an active device having first, second and third terminals, a plurality of micro-stripline resonators coupled together to form a coupled-resonator network, the coupled-resonator network being coupled to the second terminal of the active devic... | 04/29/2008 |
| 7358776 | Signal detection circuit and signal detection method It is intended to provide a signal detection circuit and a signal detection method capable of preventing influences of variations in transistor characteristics, occurrence of yield degradations of the signal detection circuit and capable of detecting differential in... | 04/15/2008 |
| 7353011 | Method and apparatus for operating a PLL for synthesizing high-frequency signals for wireless communications A method and apparatus for synthesizing high-frequency signals, such as wireless communication signals, includes a phase-locked loop (PLL) frequency synthesizer with a variable capacitance voltage controlled oscillator (VCO) that has a discretely variable capacitanc... | 04/01/2008 |
| 7339422 | Amplifier circuit and display device Offset canceling amplifier circuit in which a high accuracy of output with a suppressed output offset is achieved and a variation in a slew rate is also suppressed, and a display device having the amplifier circuit. A first differential pair (M5, M6) c... | 03/04/2008 |
| 7336106 | Phase detector and method having hysteresis characteristics A phase detector generates a first output signal if a feedback clock signal leads a reference clock signal by more than a first time. The phase detector generates a second output signal if the feedback clock signal lags the reference clock signal by more than a seco... | 02/26/2008 |
| 7336747 | Coding system for minimizing digital data bandwidth A digital compression system including a superresonant filter, which adds samples of a digital data signal at a frequency to previous samples. The added samples are parts of sine or cosine waves, not the sum of the waves. The output signal is actually the summation ... | 02/26/2008 |
| 7332950 | DLL measure initialization circuit for high frequency operation A memory device, delay lock loop circuit (DLL) and DLL reset circuitry are described. The DLL includes a shift register and a measured delay for pre-loading the shift register. The reset circuitry selectively filters a clock signal propagation through the measured d... | 02/19/2008 |
| 7332904 | On-chip resistor calibration apparatus and method An on-chip resistor is calibrated with a sense circuit that compares a resistance associated with an off-chip resistor to the on-chip resistor via a current-mirror circuit and a comparator. A digital counter circuit evaluates the comparison and adjusts its count suc... | 02/19/2008 |
| 7315599 | Skew correction circuit A skew correction circuit includes a first circuit and a second circuit. The first circuit generates at least one pulse train signal in response to a data bit signal and a first strobe signal. A duty cycle of the pulse train signal is indicative of a degree of skew ... | 01/01/2008 |
| 7310397 | Data recovery circuit, phase detection circuit and method for detecting and correcting phase conditions In the data recovery circuit of the invention, a first group of sampling clock pulses is used for sampling approximately the central portions of the data bits in an incoming data stream to produce a first sampled data stream, while a second group of sampling clock p... | 12/18/2007 |
| 7305575 | Interface circuit that interconnects a media access controller and an optical line termination transceiver module A communication system includes an interface that allows a media access controller (MAC) and an optical line termination transceiver module (TM), which have incompatible interfaces, to be connected together. The interface detects a phase relationship required by the... | 12/04/2007 |
| 7304510 | Digital phase detector improving phase detection resolution thereof A digital phase detector has a plurality of first delay elements through which a first clock is delayed, a plurality of second delay elements through which a second clock is delayed, and a plurality of data holding circuits. The data holding circuits latch the first... | 12/04/2007 |
| 7301382 | Data latch circuit and electronic device The data latch circuit of the invention includes a means for short-circuiting an input terminal and an output terminal of an inverter and by connecting the input terminal to one electrode of a capacitor and sampling a data signal or a reference potential to the othe... | 11/27/2007 |
| 7295053 | Delay-locked loop circuits A delay-locked loop (DLL) circuit comprises a voltage controlled delay line (VCDL) including a plurality of identical delay stages connected in series, and a feedback loop including a phase comparator for controlling the VCDL such that the total delay over a number ... | 11/13/2007 |
