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| Number | Title | Issue Date |
| 8179182 | Method and apparatus for clock calibration in a clocked digital device Methods and apparatuses provide a clocked digital device having dynamically adjustable operating characteristics. The digital device comprises a digital clock management (“DCM”) circuit in which the amount of delay between receipt of an active edge of a clock si... | 05/15/2012 |
| 8164376 | Clock frequency diffusing device A clock frequency diffusing device including a multiphase clock signal generator, a random number generator, signal selectors, and a clock signal generator. The multiphase clock signal generator receives an input clock signal and produces a plurality of delayed cloc... | 04/24/2012 |
| 8093937 | Seamless coarse and fine delay structure for high performance DLL A clock synchronization system and method avoids output clock jitter at high frequencies and also achieves a smooth phase transition at a boundary of coarse and fine delays. The system may use a single coarse delay line configured to generate two intermediate clocks... | 01/10/2012 |
| 8044697 | Per die temperature programming for thermally efficient integrated circuit (IC) operation Methods and apparatus to provide per die temperature programming for thermally efficient integrated circuit (IC) operation are described. In some embodiments, the junction temperature of an IC component is determined, e.g., to reduce power consumption and/or improve... | 10/25/2011 |
| 7928791 | Method and apparatus for clock calibration in a clocked digital device Methods and apparatuses provide a clocked digital device having dynamically adjustable operating characteristics. The digital device comprises a digital clock management (“DCM”) circuit in which the amount of delay between receipt of an active edge of a clock si... | 04/19/2011 |
| 7906999 | Self-protecting core system The present invention is applicable to an electronic device including a master, a slave, a bus coupling the master and the slave and a clock generator for providing a system clock to the master and slave. The clock generator determines whether the received data is c... | 03/15/2011 |
| 7872516 | Precision pulse generator A pulse generator circuit. The pulse generator circuit includes a precharge circuit coupled to receive a clock signal alternating between a first logic level and a second logic level, a storage circuit having a storage node, wherein the precharge circuit is configur... | 01/18/2011 |
| 7872517 | Bus circuit Clock control is handed over in a bus circuit from a first circuit (14) to a second circuit (12). A clock conductor (10a) is driven to a predetermined voltage level with the driver circuit of the first circuit after a last clock period fo... | 01/18/2011 |
| 7804349 | Timing signal generator providing synchronized timing signals at non-integer clock multiples adjustable by more than one period A system for providing a plurality of synchronous timing signals having period values that are not even multiples of the clock period including a plurality of local edge generators receiving the clock signals, each local generator including local programmable means ... | 09/28/2010 |
| 7746144 | Pulse generator and method of generating pulses, such as for template generation in impulse radio systems The pulse generator comprises: a delay line arranged to receive a digital input signal and to produce a plurality of delay line output signals; first and second pulse generator blocks comprising logic circuitry arranged to generate a plurality of successive first ou... | 06/29/2010 |
| 7724060 | Interface circuit and a clock output method therefor An interface circuit outputting a clock signal and data to a data register configured to serially read in the data synchronously with the clock signal, in response to a change of a control signal for outputting the clock signal and the data from one logic level to t... | 05/25/2010 |
| 7724059 | Clock scaling circuit Techniques for scaling and switching clocks in a glitch-free manner are provided. For example, in one aspect of the present invention, a technique for switching a frequency associated with a master clock includes the following steps/operations. Two phase clocks are ... | 05/25/2010 |
| 7705652 | Clock generating apparatus and clock generating method A clock generating apparatus has an integral ratio divider for, according to frequency-dividing parameters for generating a second clock signal including a second frequency by using a first clock signal including a first frequency, outputting the second clock signal... | 04/27/2010 |
| 7683692 | Bus circuit Clock control is handed over in a bus circuit from a first circuit (14) to a second circuit (12). A clock conductor (10a) is driven to a predetermined voltage level with the driver circuit of the first circuit after a last clock period fo... | 03/23/2010 |
| 7675341 | Method and device for generating a clock signal A method and device for generating a clock signal, the method including measuring, using a first clock signal, a characteristic of a reference event in a received signal, determining, using the first clock signal, a variation of a characteristic of a second event in... | 03/09/2010 |
| 7557632 | Internal clock generator and method of generating internal clock An internal clock generator includes a detector, an internal signal generator and a clock output unit. The detector detects a transition point of an external clock signal and outputting a detection signal. The internal signal generator generates an internal signal i... | 07/07/2009 |
| 7466180 | Clock network A clock network comprises a clock distribution path coupled to a circuit. The clock distribution path and the circuit are formed on a substrate. The clock distribution path comprises a plurality of interconnected elements and one or more disconnected elements. The d... | 12/16/2008 |
| 7463077 | Device for generating a periodic clock signal A device for generating a periodic clock signal according to the invention comprises a bandpass filter is disclosed. In one embodiment, the bandpass filter includes a bandpass filter input for receiving an input signal and a bandpass filter output for outputting a b... | 12/09/2008 |
| 7446589 | Pulse generation circuit Pulse generation circuit has a P-MOS transistor having a drain electrode connected to a first power source; a first N-MOS transistor having a drain electrode connected to the source electrode of the P-MOS transistor; a second N-MOS transistor having a drain electrod... | 11/04/2008 |
| 7427879 | Frequency detector utilizing pulse generator, and method thereof The present invention discloses a frequency detecting apparatus for detecting a frequency of an input clock. The frequency detecting apparatus includes: a pulse generator, a digital signal generator, and a decoder. The pulse generator is coupled to the input clock f... | 09/23/2008 |
| 7427885 | Semiconductor device having a power supply capacitor In order to prevent a signal of a signal wiring from receiving a bad influence due to a power supply capacitor, provided is a semiconductor including a high reference potential terminal and a low reference potential terminal composing power supply voltage terminals;... | 09/23/2008 |
| 7425859 | Apparatus and method for generating pulses An apparatus for generating pulses includes: (a) A delay unit having an input delay locus for receiving a delay unit input signal and an output delay locus for presenting an output delay signal. The delay unit output signal is delayed by a delay interval with respec... | 09/16/2008 |
| 7411427 | Clock input filter circuit A clock input filter uses a first programmable low-pass delay element to filter during a low period of an input clock signal and to output a SET signal. The clock input filter uses a second programmable low-pass delay element to filter during a high period of the in... | 08/12/2008 |
| 7378893 | Circuit and method for digital delay and circuits incorporating the same A method includes generating multiple delayed versions of a first signal using at least one first delay line, selecting at least one version of the first signal, and generating a second signal based on the at least one selected version of the first signal. The metho... | 05/27/2008 |
| 7356076 | System and method supporting auto-recovery in a transceiver system A method and apparatus are disclosed to aid a transceiver chip, in a serial data communications system, in recovering from a system-side, out-bound data clocking problem. If a problem with a primary clock signal, used to clock data from a system-side of a transceive... | 04/08/2008 |
| 7352218 | DLL circuit and method of controlling the same A DLL circuit includes a buffer control unit configured to detect whether or not a DLL power supply exceeds a reference level and output a buffer control signal. A clock buffer buffers an external clock to generate an internal clock when the buffer control signal is... | 04/01/2008 |
| 7340313 | Monitoring device for monitoring internal signals during initialization of an electronic circuit The invention provides a device for monitoring electronic circuit units during an initialization phase. The device has at least one internal data line (103) for forwarding internal data (105) in the electronic circuit unit (101) and at least one... | 03/04/2008 |
| 7339412 | Digital clock generator The invention relates to a clock generator comprised of a system clock input (2) for applying a high-frequency system clock signal, of a digital input (3) for applying a settable digital increment value, of an adder (6) for adding the increment ... | 03/04/2008 |
| 7339405 | Clock rate adjustment apparatus and method for adjusting clock rate A clock rate adjustment apparatus and a method for adjusting a clock rate of a clock for an optical storage system are provided. The clock rate adjustment apparatus comprises an indication provider, a throughput rate detector, and a clock generator. The method perfo... | 03/04/2008 |
| 7339413 | Clock generator and organic light emitting display (OLED) including the clock generator A clock generator, which can be included in an Organic Light Emitting Display (OLED), includes four switching units and two inverters. Each of the switching units includes two transistors. Transistors of two switching units that are connected to a high-level voltage... | 03/04/2008 |
| 7319355 | Pulse generator A system for generating a pulse signal in response to a clock signal includes a latch module for generating a latched output in response to a leading edge of the clock signal. A delay module is coupled to the latch module for delaying the latched output. A first log... | 01/15/2008 |
| 7315469 | Control of set/reset pulse in response to peripheral temperature in PRAM device A drive circuit for a PRAM (phase-change random access memory) device includes a write driver that generates a set/reset current in response to a set/reset pulse. In addition, a temperature compensator controls a pulse width of the set/reset pulse in response to a p... | 01/01/2008 |
| 7304522 | Spread spectrum clock generator A spread spectrum clock generator includes a plurality of delay cells, wherein each delay cell includes at least one delayer receiving an external clock signal and causing a predetermined propagation delay to the received clock signal, and a controller transmitting ... | 12/04/2007 |
| 7301384 | Multimode, uniform-latency clock generation circuit A multimode, uniform-latency clock generation circuit (CGC) is described herein. In one example, the multimode, uniform-latency CGC generates a pulse clock signal via a clock generation path responsive to a clock chopping signal being active and generates a phase cl... | 11/27/2007 |
| 7296173 | Semiconductor integrated circuit A semiconductor integrated circuit is provided in which the timing margin for fetching data is prevented from being reduced even in the case where the duty ratio of a clock signal is different from 50%. The semiconductor integrated circuit includes: a clock input te... | 11/13/2007 |
| 7295044 | Receiver circuits for generating digital clock signals A digital clock generation circuit (and a method for operating the same). The digital clock generation circuit includes a first, a second, a third differential comparator circuits. The first differential comparator circuit receives the positive differential clock si... | 11/13/2007 |
| 7279950 | Method and system for high frequency clock signal gating A differential clock signal gating method and system is provided, wherein a clock buffer circuit control path develops a clock gating signal with a timing relationship to a clock signal. The clock gating signal gates a buffer on the clock buffer circuit controlled p... | 10/09/2007 |
| 7274240 | Clock control cell A clock control cell for production of an output clock signal from an input clock signal has a hold element and an output stage. The hold element is preceded by a signal level converter, with the signal level converter designed such that it converts an input signal ... | 09/25/2007 |
| 7272196 | Adjustable phase controlled clock and data recovery circuit A clock and data recovery circuit including: means for generating a first and a second clock signal; means for receiving the first clock signal and for generating a third clock signal from the first clock signal and means for receiving the second clock signal and fo... | 09/18/2007 |
| 7262640 | Voltage-frequency conversion apparatus A voltage-frequency conversion apparatus which has a variable current source for charging a capacitor; a current amount adjustment unit that adjusts a current amount of the variable current source for charging the capacitor to be corresponding to a differential volt... | 08/28/2007 |
