Quotables
"Flight by machines heavier than air is unpractical and insignificant, if not utterly impossible."
Simon Newcomb, astronomer ; Said in 1902, less than two years before the first flight at Kitty Hawk
PatentStorm News
Make the Most of Our Site
See this month's Top Inventors and Most Cited Patents.
Stay on top of the latest innovations by subscribing to an RSS feed.
Registered users: Manage your profile.
| Number | Title | Issue Date |
| 7952414 | Phase clock generator Disclosed is a phase clock generator. The phase clock generator can include transistors and a buffer. The transistors are connected between a power line and a grounding line and are provided in a form of a 4×N matrix to receive a plurality of phase-delayed signals ... | 05/31/2011 |
| 7936199 | Apparatus and method for external to internal clock generation A phase recombination circuit includes a first phase input and a first one-shot pulse generator adapted to receive the first phase input and produce a first signal to pull a signal to a first state. The phase recombination circuit also includes a second phase input ... | 05/03/2011 |
| 7936200 | Apparatus and method for providing a clock signal A clock circuit which may include a first clock input for receiving a first clock signal and a second clock input for receiving a second clock signal. A clock calibration unit is connected to the first clock input and the second clock input. The calibration unit may... | 05/03/2011 |
| 7893748 | Glitch-free clock multiplexer that provides an output clock signal based on edge detection Clock multiplexing techniques generate an output clock signal by detecting edges of a selected input clock signal and toggling the output clock signal based on detected edges of the selected input clock signal. Toggle signals are generated based on detected edges of... | 02/22/2011 |
| 7688128 | Digital imaging chip using an analog clock signal as a provisional clock signal A method of operating an imaging system, the imaging system including a plurality of subsets of imaging elements, such as photosensors, light emitters, or ink-jet ejectors. The imaging elements use a regular clock signal for operation. A provisional clock signal, su... | 03/30/2010 |
| 7688129 | System and method for open-loop synthesis of output clock signals having a selected phase relative to an input clock signal Delay circuits are used in a manner similar to a synchronized mirror delay circuit to generate a quadrature clock signal from an input clock signal. The input clock signal is coupled through a series of first delay circuit for one-half the period of the input clock ... | 03/30/2010 |
| 7659764 | Efficient delay elements Circuits, methods, and apparatus for delaying signals in a power and area efficient manner are provided. A gating element within a stage of a programmable delay element suppresses an operation of other stages of the delay element. A programmable delay has components... | 02/09/2010 |
| 7656216 | Method and system for determining a clock input mode A method and system is provided for clock input mode selection. When a signal provided on one of two clock input terminals is received, the received signal is considered in connection with a second input signal in order to determine whether the first input signal an... | 02/02/2010 |
| 7629829 | Phase mixing device for use in duty cycle correction Disclosed is a duty cycle correction device for correcting a duty cycle of a clock signal output from a delay locked loop circuit. The duty cycle correction device includes a mixer for mixing phases of the first and second clock signals, thereby outputting a first s... | 12/08/2009 |
| 7629828 | Glitch-free clock multiplexer that provides an output clock signal based on edge detection Clock multiplexing techniques generate an output clock signal by detecting edges of a selected input clock signal and toggling the output clock signal based on detected edges of the selected input clock signal. Toggle signals are generated based on detected edges of... | 12/08/2009 |
| 7626438 | Circuit to switch between clock signals and related method An embodiment of a circuit switches between at least a first clock signal and a second clock signal in response to a corresponding switch command, and includes a selection module to select at a switch instant said second clock signal under the control of a signal se... | 12/01/2009 |
| 7626437 | Circuit assembly for converting a differential input clock signal pair into a single-ended output clock signal A circuit assembly for converting a differential input clock signal pair into a single-ended output clock signal comprises a NMOS differential amplifier (20) including two N-channel field-effect transistors (N1, N2) which converts the input cloc... | 12/01/2009 |
| 7586356 | Glitch free clock multiplexer that uses a delay element to detect a transition-free period in a clock signal A clock multiplexer circuit uses a delay element to detect a transition-free period in a first signal present on a D-input lead of an output latch. The output latch is then controlled to latch the stable value of the first signal, and to hold the value of the first ... | 09/08/2009 |
| 7501872 | Clock-generator architecture for a programmable-logic-based system on a chip A programmable system-on-a-chip integrated circuit device comprises at least one of a crystal oscillator circuit, an RC oscillator circuit, and an external oscillator input. A clock conditioning circuit is selectively coupleable to one of the programmable logic bloc... | 03/10/2009 |
| 7456675 | Semiconductor integrated circuit device for preventing generation of irregular clock signal A disclosed semiconductor integrated circuit device includes a selection circuit that is supplied with a first clock signal and a second clock signal, a selection signal, and a switching signal, and configured to select one of the first clock signal and the second c... | 11/25/2008 |
| 7446588 | Highly scalable methods and apparatus for multiplexing signals In a first aspect, a first method is provided that includes providing a plurality of select signals and a plurality of input signals for input by a multiplexer. Each select signal is adapted to cause the multiplexer to select a different one of the plurality of inpu... | 11/04/2008 |
| 7427881 | Clock loss detection and switchover circuit In one aspect, an embodiment provides a clock loss sense and switchover circuit and method in which clock switchover is responsive to loss of a primary signal and to additional switch command signaling. In another aspect, an embodiment provides a clock loss sense ci... | 09/23/2008 |
| 7425859 | Apparatus and method for generating pulses An apparatus for generating pulses includes: (a) A delay unit having an input delay locus for receiving a delay unit input signal and an output delay locus for presenting an output delay signal. The delay unit output signal is delayed by a delay interval with respec... | 09/16/2008 |
| 7397294 | Charge pump clock generating circuit and method thereof A charge pump clock generating circuit and a method thereof are disclosed. The circuit includes a sync counter, a comparator, and a clock generating circuit. The sync counter receives a dot clock and a reset signal for accumulating a counting value according to the ... | 07/08/2008 |
| 7378893 | Circuit and method for digital delay and circuits incorporating the same A method includes generating multiple delayed versions of a first signal using at least one first delay line, selecting at least one version of the first signal, and generating a second signal based on the at least one selected version of the first signal. The metho... | 05/27/2008 |
| 7375571 | Glitch free clock multiplexer that uses a delay element to detect a transition-free period in a clock signal A clock multiplexer circuit uses a delay element to detect a transition-free period in a first signal present on a D-input lead of an output latch. The output latch is then controlled to latch the stable value of the first signal, and to hold the value of the first ... | 05/20/2008 |
| 7375570 | High-speed TDF testing on low cost testers using on-chip pulse generators and dual ATE references for rapidchip and ASIC devices A circuit which facilitates TDF testing without having to purchase expensive new test equipment, such as a new test platform that is capable of supporting test frequencies well beyond the current 200 MHz limitation. A solution to current TDF testing problems by addi... | 05/20/2008 |
| 7372312 | Pulse width modulation generating circuit A pulse width modulation (PWM) generating circuit includes a first comparator, a first resistor, a second resistor, a third resistor, a fourth resistor, a capacitor, and a diode. The first resistor and the second resistor are connected in series between a voltage in... | 05/13/2008 |
| 7373536 | Fine granularity halt instruction Systems and methods for halting the execution of instructions in a microprocessor are disclosed. The halt instruction may have an operand which allows a programmer to specify which clock of a system is to be utilized in conjunction with the halt instruction. A speci... | 05/13/2008 |
| 7368958 | Methods and systems for locally generating non-integral divided clocks with centralized state machines A method for locally generating a ratio clock on a chip includes generating a global clock signal having a global clock cycle. A centralized state machine includes a counter going through a complete cycle in response to a non-integer number of global clock cycles, t... | 05/06/2008 |
| 7365565 | Programmable system on a chip for power-supply voltage and current monitoring and control A programmable system-on-a-chip integrated circuit device includes a programmable logic block, at least one user non-volatile memory block, and voltage-measuring and control analog and digital circuits on a single semiconductor integrated circuit chip or a flip chip... | 04/29/2008 |
| 7362835 | Clock generator circuit and related method for generating output clock signal The present invention discloses a clock generator circuit for generating an output clock signal. The clock generator circuit includes: a random frequency code generator for generating a frequency code randomly, wherein the random frequency code generator is clocked ... | 04/22/2008 |
| 7355460 | Method for locally generating non-integral divided clocks with centralized state machines A method for locally generating a ratio clock on a chip includes generating a global clock signal having a global clock cycle. A centralized state machine is provided that includes a counter going through a complete cycle in response to a non-integer number of globa... | 04/08/2008 |
| 7352224 | Pulse generator and method for generating a pulse train A method for generating a pulse train is provided with adjustable start and end times of individual pulses, in which additional clock signals are generated from a 0th clock signal, the signals which in each case have a frequency of the 0th clock signal and whose pha... | 04/01/2008 |
| 7352206 | Integrated circuit device having state-saving and initialization feature An integrated circuit device has a state-saving feature and includes a programmable logic block, I/O pads, a dedicated register, at least one volatile memory block, a non-volatile memory block, a condition-sensing circuit for detecting at least one condition, A cont... | 04/01/2008 |
| 7350096 | Circuit to reduce power supply fluctuations in high frequency/ high power circuits The present invention provides for a circuit for transitioning clocking speeds. A counter is coupled to the clocking means. A comparator is coupled to an output of the counter. A first divider is coupled to the output of the counter. A processor means is coupled to ... | 03/25/2008 |
| 7343504 | Micro controller unit (MCU) with RTC A microcontroller unit (MCU) is disclosed with a stand-alone Real Time Clock (RTC). The MCU includes a processing circuit for receiving digital information and processing said received digital information. A primary clock circuit provides the timing for the processi... | 03/11/2008 |
| 7336116 | Clock supply circuit The clock supply circuit of the present invention comprises a plurality of clock supply paths and a clock gate circuit. The clock supply paths branch a clock signal and supply each of the branched clock signals to a plurality of sequential circuits via a buffer. The... | 02/26/2008 |
| 7334152 | Clock switching circuit A clock switching circuit comprises: a composite clock generation circuit, which is to receive a first clock, a second clock, and a clock switching execution signal for switching between the first clock and the second clock, and to make a level of the clock fixed to... | 02/19/2008 |
| 7333527 | EMI reduction using tunable delay lines The clock signal is the dominant source of electromagnetic interference (EMI) for many digital electronic devices. EMI generated by these electronic devices must be suppressed to avoid interference with other electronic devices and to satisfy FCC regulations. The pr... | 02/19/2008 |
| 7324667 | Data converter A data converter is provided, which data converter includes a data conversion unit, a timer unit which counts time, and a lock system which locks a data conversion function of the data conversion unit in a disabled state based on the time counted by the timer unit. | 01/29/2008 |
| 7321244 | Clock switching device and clock switching method A clock switching device capable of automatic switching to a clock distribution system for back-up without interrupting processing of the device, which includes an abnormality detection unit which detects lack of coincidence in a logical level between a current cloc... | 01/22/2008 |
| 7319348 | Circuits for locally generating non-integral divided clocks with centralized state machines Circuitry for locally generating a ratio clock on a chip. The circuitry includes circuitry for generating a global clock signal having a global clock cycle. A state machine includes a counter going through a complete cycle in response to a non-integer number of glob... | 01/15/2008 |
| 7320082 | Power control system for synchronous memory device A memory device with multiple clock domains. Separate clocks to different portions of the control circuitry create different clock domains. The different domains are sequentially turned on as needed to limit the power consumed. The turn on time of the domains is ove... | 01/15/2008 |
| 7319344 | Pulsed flop with embedded logic In one embodiment, an apparatus comprises a logic circuit, a plurality of passgates, at least one pulse generator, and a plurality of latch elements. The logic circuit has a plurality of inputs, and each of the passgates has an output directly connected to one of th... | 01/15/2008 |
