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| Number | Title | Issue Date |
| 7876144 | Start-up circuit and start-up method A start-up circuit receives a start-up signal instructing start-up of an equipment mounted with the circuit, and executes a predetermined sequence when start-up is instructed by the start-up signal. An oscillator generates a clock signal. A sequence circuit receives... | 01/25/2011 |
| 7750715 | Charge-sharing method and device for clock signal generation A clock generation circuit has two output ends to provide a first clock signal and a second clock signal, in response to first and second input signals, respectively. A charge storage component is used to transfer some charge from the first output end to the charge ... | 07/06/2010 |
| 7586355 | Low skew clock distribution tree A clock distribution tree for an integrated circuit memory includes a set of data drivers, a corresponding set of input buffers coupled to the data drivers, a first clock distribution tree coupled to the data drivers, and a second clock distribution tree coupled to ... | 09/08/2009 |
| 7411437 | Triggering events at fractions of a clock cycle Generally, the embodiments presented are directed to circuits and methods for triggering an event at a fraction of a clock cycle. A triggering circuit can comprise two or more input circuits that output an event signal. The event signal is received by one of two or ... | 08/12/2008 |
| 7385430 | Data output clock generating circuit and method of generating data output clock of semiconductor memory apparatus A data output clock generating circuit for a semiconductor memory apparatus includes a rising data output clock generating unit which combines a rising clock with a signal to be generated in response to a rising output enable signal and a falling clock to generate a... | 06/10/2008 |
| 7378894 | Method and system for clock routing and compensation A method, apparatus, article of manufacture, and system, the method including, in some embodiments, providing a differential clock ganging structure to receive complementary differential clock signals, the differential clock ganging structure outputting clock gangin... | 05/27/2008 |
| 7362834 | Method and device for synchronizing at least one node of a bus system and a corresponding bus system Method of synchronizing at least one user of a bus system which is operated with a preselectable system clock period (NTU), a local clock period (LNTU) and a reference clock period (GNTU) being preselected for the at least one user, and the reference clock period (G... | 04/22/2008 |
| 7337419 | Crosstalk noise reduction circuit and method In a semiconductor device, a method for reducing the effect of crosstalk from an aggressor line to a victim line begins with sensing the occurrence of a voltage change on the aggressor line that can induce a voltage pulse having a pulse magnitude that exceeds a puls... | 02/26/2008 |
| 7327181 | Multiple phase simultaneous switching preventing circuit, PWM inverter and its driving method A PWM inverter in which high-surge voltage is not applied across terminals of a switching device thereof is provided by preventing multi-phase simultaneous switching. A multi-phase simultaneous-switching prevention circuit (100) that includes: a plurality of ... | 02/05/2008 |
| 7302599 | Instantaneous frequency-based microprocessor power management A power management controller for instantaneous frequency-based microprocessor power management including first and second PLLs, select logic, and source control logic. The first PLL generates a first core source clock signal at a first frequency based on a bus cloc... | 11/27/2007 |
| 7295049 | Method and circuit for rapid alignment of signals Circuits and methods for aligning two or more signals including a first and second signal. In one embodiment, a shift register generates two or more shifted copies of the second signal, and each of a plurality of phase detectors receives the first signal and one of ... | 11/13/2007 |
| 7290156 | Frequency-voltage mechanism for microprocessor power management A frequency-voltage mechanism for power management including first and second PLLs, select logic, control logic, and voltage control logic. The first PLL generates a first source clock signal at a first frequency based on a bus clock signal. The second PLL generates... | 10/30/2007 |
| 7274228 | Method and apparatus for digital phase generation at high frequencies An apparatus and method for generating phase related clocks, includes delaying a clock input by a cycle delay magnitude to generate a cycle delay signal and N delay taps is disclosed. Each delay tap has a delay equal to a fractional amount of the cycle delay magnitu... | 09/25/2007 |
| 7268409 | Spiral inductor with electrically controllable resistivity of silicon substrate layer A microelectronic device including, in one embodiment, a plurality of active devices located at least partially in a substrate, at least one dielectric layer located over the plurality of active devices, and an inductor located over the dielectric layer. At least on... | 09/11/2007 |
| 7269094 | Memory system and method for strobing data, command and address signals A memory system couples command, address or write data signals from a memory controller to a memory device and read data signals from the memory device to the memory controller. A respective strobe generator circuit in each of the memory controller and the memory de... | 09/11/2007 |
| 7253674 | Output clock phase-alignment circuit A clock generator has a reset circuit and (at least) two dividers, where each divider divides a reference clock signal by a divisor value to generate an output clock signal. The reset circuit generates reset signals for the dividers, where the reset signals are dela... | 08/07/2007 |
| 7251194 | Memory system and method for strobing data, command and address signals A memory system couples command, address or write data signals from a memory controller to a memory device and read data signals from the memory device to the memory controller. A respective strobe generator circuit in each of the memory controller and the memory de... | 07/31/2007 |
| 7248848 | Communication apparatus including dual timer units A communication apparatus includes a radio frequency circuit that operates on a radio frequency signal and a digital processing circuit coupled to the radio frequency circuit. The digital processing circuit includes a first timing circuit that provides timed signals... | 07/24/2007 |
| 7245240 | Integrated circuit serializers with two-phase global master clocks Integrated circuit serializer circuitry is provided that converts parallel data to serial data on an integrated circuit. A two-phase global serializer master clock generator uses a four-phase internal clock to generate a two-phase global serializer master clock. The... | 07/17/2007 |
| 7245553 | Memory system and method for strobing data, command and address signals A memory system couples command, address or write data signals from a memory controller to a memory device and read data signals from the memory device to the memory controller. A respective strobe generator circuit in each of the memory controller and the memory de... | 07/17/2007 |
| 7242261 | Voltage control for clock generating circuit An apparatus is provided that includes a clock distribution network, a plurality of distributed oscillators provided about the clock distribution network so as to provide clock signals on the clock distribution network and a power control circuit to control power ap... | 07/10/2007 |
| 7215594 | Address latch circuit of memory device An address latch circuit of a memory device is disclosed. A latch operation is disabled while an address signal makes a level transition in the memory device, and then enabled when the address signal is stabilized after the level transition. Therefore, it is possibl... | 05/08/2007 |
| 7202721 | Delay locked loop and semiconductor memory device having the same In a delay locked loop and a semiconductor memory device having the same, the delay locked loop includes a phase detecting and control signal generator for detecting a phase difference between a clock signal and a feedback clock signal and generating a plural-bit de... | 04/10/2007 |
| 7197659 | Global I/O timing adjustment using calibrated delay elements A method transfers a signal from a transmitting device to a receiving device. The signal is output from the transmitting device using a driving circuit. A reference clock signal is received in the transmitting device. An output clock signal is generated according to... | 03/27/2007 |
| 7194057 | System and method of oversampling high speed clock/data recovery A system and method of high speed clock/data recovery, which is used to recover the high speed clock/data through oversampling technique, wherein the internal clock with frequency lower than the high speed data is used for data recovery. Only three clocks are used i... | 03/20/2007 |
| 7190209 | Low-power high-performance integrated circuit and related methods An integrated circuit is provided which includes a multi-state circuit with a first PMOS transistor and a first NMOS transistor. In an active mode, the multi-state circuit is operable to switch between a first state in which the first PMOS transistor is turned on an... | 03/13/2007 |
| 7187617 | Memory system and method for strobing data, command and address signals A memory system couples command, address or write data signals from a memory controller to a memory device and read data signals from the memory device to the memory controller. A respective strobe generator circuit in each of the memory controller and the memory de... | 03/06/2007 |
| 7184342 | Semiconductor memory device having enhanced sense amplifier Disclosed is a semiconductor memory device with a reduced write recovery time and an increased refresh period. The semiconductor memory device incorporating a plurality of memory cells therein, including: a bit line sense amplifier (BLSA) array provided with a plura... | 02/27/2007 |
| 7158904 | System and method for correcting an inaccurate clock System and method for correcting an inaccurate clock with the use of an accurate reference clock. A preferred embodiment comprises repeatedly counting clock cycles in a clock signal generated by the inaccurate clock for a specified period of time, after the completi... | 01/02/2007 |
| 7142033 | Differential clocking scheme in an integrated circuit having digital multiplexers A system for distributing a small signal differential signal to a circuit element. The system includes: a first converter configured to convert a first small signal differential signal to a first two phase full CMOS differential signal for input into the differentia... | 11/28/2006 |
| 7139345 | Method and circuit for adjusting the timing of output data based on the current and future states of the output data A clock synchronization circuit receives an input clock signal along with current and future data signals. The clock synchronization circuit generates a phase shifted clock signal in response to the input clock signal, with the phase shifted clock signal having a ph... | 11/21/2006 |
| 7135907 | Clock signal distribution utilizing differential sinusoidal signal pair A differential sinusoidal signal pair is generated on an integrated circuit (IC). The differential sinusoidal signal pair is distributed to clock receiver circuits, which may be differential amplifiers. The clock receiver circuits receive the differential sinusoidal... | 11/14/2006 |
| 7136441 | Clock recovery circuit A driver and a receiver supply a data signal, which is based on serial data having a regular bit pattern, such as a clock, which includes 1's and 0's alternating with each other during an adjustment period, and is based on serial data having an arbitrary bit pattern... | 11/14/2006 |
| 7126874 | Memory system and method for strobing data, command and address signals A memory system couples command, address or write data signals from a memory controller to a memory device and read data signals from the memory device to the memory controller. A respective strobe generator circuit in each of the memory controller and the memory de... | 10/24/2006 |
| 7126406 | Programmable logic device having an embedded differential clock tree A clock distribution network having: a backbone clock signal line configured to provide a differential clock signal; multiple branches coupled to the backbone clock signal line for distributing the differential clock signal to multiple programmable function elements... | 10/24/2006 |
| 7116322 | Display apparatus and controlling method thereof A display apparatus comprises input parts through which analog and digital video signals outputted from a video card are inputted, and a plurality of driving components. The apparatus further comprises: an electric power supply part for supplying electric power; a s... | 10/03/2006 |
| 7107477 | Programmable logic devices with skewed clocking signals A programmable logic device has programmable phase-shifting circuitry. The phase-shifting circuitry is used to generate a set of skewed clock signals that is used to adjust the relative timing of device elements in a circuit synthesized in the programmable logic dev... | 09/12/2006 |
| 7103126 | Method and circuit for adjusting the timing of output data based on the current and future states of the output data A clock synchronization circuit receives an input clock signal along with current and future data signals. The clock synchronization circuit generates a phase shifted clock signal in response to the input clock signal, with the phase shifted clock signal having a ph... | 09/05/2006 |
| 7081777 | Multiple-phase switching circuit A multiple-phase switching circuit includes an alternative signal generator for generating a plurality of alternative signals according to a switching signal, and a multiplexer for receiving a plurality of clock signals and outputting a target clock signal according... | 07/25/2006 |
| 7071756 | Clock multiplexing system A clock control circuit in an integrated circuit for providing a differential clock signal to a differential clock tree. The clock control circuit includes: first differential multiplexers configured to select first outputs from the input clock signals; second diffe... | 07/04/2006 |
