Did You Know...
...that in the early 1940s GE engineer James Wright was charged with a task of utmost importance to the war effort: develop a cheap substitute for rubber that could be used to produce tires, gas masks and a whole host of military gear. Wright tackled the task diligently -- and wound up inventing Silly Putty.
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| Number | Title | Issue Date |
| 8188782 | Clock system and method for compensating timing information of clock system A clock system includes a clock signal generating circuit and a controlling circuit. The clock signal generating circuit is used for generating a primary clock signal and a reference clock signal both derived from an oscillating signal of the clock signal generating... | 05/29/2012 |
| 8149040 | Apparatus for generating a plurality of different voltage level clock signals A system is provided for generating a plurality of different voltage level clock signals. The system comprises an electrical energy storage pack having a plurality of series coupled electrical energy storage cells that provide a plurality of different output voltage... | 04/03/2012 |
| 8049548 | Digital synchronous circuit A digital synchronous circuit includes a clock generator for generating a reference clock signal, a plurality of delays for delaying the reference clock signal by predetermined different times, a transition varying buffer for controlling input transitions of the clo... | 11/01/2011 |
| 7999594 | Semiconductor integrated circuit and control signal distribution method A semiconductor integrated circuit includes a plurality of areas, each of which generates phase clocks in accordance with an external clock and control signals and performs a predetermined process assigned to each of the phase clocks. The semiconductor integrated ci... | 08/16/2011 |
| 7990200 | Pulse width modulation control system A PWM control system includes a multi-phase PWM controller and at least one single-phase PWM controller. The multi-phase PWM controller is capable of generating a multi-phase PWM signal. The at least one single-phase PWM controller is capable of generating a single-... | 08/02/2011 |
| 7956665 | Methods and articles of manufacture for operating electronic devices on a plurality of clock signals Embodiments of the invention relate to an integrated circuit comprising at least one functional unit configured to operate at a first clock frequency. The integrated circuit also comprises at least one first interconnect originating from a contact pad and leading to... | 06/07/2011 |
| 7952413 | Clock generating circuit and clock generating method thereof A clock generating circuit, including a pulse generating unit to generate a plurality of pulse signals based on a reference clock, the pulse signals each having the same period, a phase difference between the adjacent pulse signals being a first phase difference; an... | 05/31/2011 |
| 7920008 | Data output clock generating circuit and method of generating data output clock of semiconductor memory apparatus A data output clock generating circuit for a semiconductor memory apparatus includes a rising data output clock generating unit configured to combine a rising clock with a rising clock extraction signal generated in response to a rising output enable signal and a fa... | 04/05/2011 |
| 7911253 | Hybrid clock network Some of the embodiments of the present invention provide an integrated circuit device including a clock distribution network, the clock distribution network comprising an inner band, an outer band, and a clock distribution tree including a plurality of stages, each ... | 03/22/2011 |
| 7834675 | Clock control circuit and semiconductor memory device using the same A clock control circuit comprises a control signal generating unit configured to generate a control signal disabled in a predetermined state while in an active mode, and a clock transferring unit configured to transfer an external clock in response to the control si... | 11/16/2010 |
| 7821317 | Clock generating apparatus A clock generating apparatus includes a clock generator and a controllable delay line. The clock generator receives an external clock signal and generates multiple clock signals having different phases by delaying the external clock signal. The controllable delay li... | 10/26/2010 |
| 7808293 | Clock distribution circuit A clock distribution circuit includes a monitoring circuit that delays a signal based on a clock signal from a clock tree by using multiple inverter circuits and predicts a timing violation on the basis of the amount of delay produced by the multiple inverter circui... | 10/05/2010 |
| 7795943 | Integrated circuit device and layout design method therefor An integrated circuit device has multiple first circuit elements arranged in a first area. A signal distribution circuit that has multiple drive circuits is connected in the form of a tree structure and that distributes a common signal that is input to the starting ... | 09/14/2010 |
| 7791394 | Decentralised fault-tolerant clock pulse generation in VLSI chips The invention relates to a method for distributed, fault-tolerant clock pulse generation in hardware systems, wherein the system clock pulse is generated in distribution by a plurality of intercommunicating fault-tolerant clock pulse synchronization algorithms (TS-A... | 09/07/2010 |
| 7786786 | Multiphase clock for superconducting electronics A multiphase clock circuit in which bit errors are propagated only for the duration of the clock cycle in which a bit error occurs. The circuit recovers automatically from bit errors and is capable of operating at high frequency with high clock precision. The multip... | 08/31/2010 |
| 7760002 | Clock generating circuit and clock generating method thereof A clock generating circuit, including a pulse generating unit to generate a plurality of pulse signals based on a reference clock, the pulse signals each having the same period, a phase difference between the adjacent pulse signals being a first phase difference; an... | 07/20/2010 |
| 7760001 | Signal processing apparatus The real number counter subtracts the positive integer C if the count value RC is equal to or larger than 0, or adds (the positive integer B-C) and outputs a Carry if the count value RC is negative. The first integer counter for generating the first clock f1 ... | 07/20/2010 |
| 7701276 | Multi-phase negative delay pulse generator A multi-phase pulse generator provides an even number of pulse signals of same phase difference and pulse signals of higher frequency by applying a negative delay concept. The multi-phase pulse generator includes a first delay block with first unit blocks which have... | 04/20/2010 |
| 7675340 | Multiphase clock generator circuit A multiphase clock generator circuit for generating a plurality of output clock pulses that differ in phase on the basis of a reference clock pulse, has first and second divider circuits for dividing first and second reference clock pulses that differ in phase to ge... | 03/09/2010 |
| 7652517 | Method and apparatus for generating synchronous clock signals from a common clock signal A method and system for generating multiple clock signals from a reference clock signal are provided. In one implementation, the system includes a reference clock to generate a reference clock signal having a first frequency, a first prescaler to receive the referen... | 01/26/2010 |
| 7629827 | Semiconductor integrated circuit The semiconductor integrated circuit includes a first subordinate clock tree 802 and a second subordinate clock tree 803, wherein a clock is delayed by a variable delay circuit 805 and inputted into the second subordinate clock tree 803 s... | 12/08/2009 |
| 7616043 | Methods and apparatus for managing LSI power consumption and degradation using clock signal conditioning Methods and apparatus for distributing clock signals to an integrated circuit provide for: producing, in a slow mode of operation, a first clock signal having at least first and second on-pulses of differing first and second on-times each period, respectively, where... | 11/10/2009 |
| 7612599 | Semiconductor device Clock skew can be reduced by suppressing fluctuation in wiring leads between the final stage clock buffers and the clock distribution circuit for supplying the clock. In view of attaining such reduction of clock skew, an upstream of the clock distribution circuit is... | 11/03/2009 |
| 7567110 | Clock distribution circuit A clock distribution circuit for distributing an input clock according to an embodiment of the present invention includes: a first clock buffer receiving the clock; a first clock mask series-connected to the first clock buffer and controlling clock input to the firs... | 07/28/2009 |
| 7567109 | Integrated circuit devices generating a plurality of drowsy clock signals having different phases An integrated circuit device which internally generates a plurality of drowsy clock signals having different phases is provided. The integrated circuit device includes a phase synchronizer configured to output a plurality of clock signals having different phases in ... | 07/28/2009 |
| 7511548 | Clock distribution network, structure, and method for providing balanced loading in integrated circuit clock trees A clock distribution network, structure, and method for providing balanced loading is disclosed. In particular, a clock distribution network may be formed of one or more clock fanout distribution levels. Each respective distribution level may include an equal number... | 03/31/2009 |
| 7492205 | Clock generator A clock generator includes a first circuit, a second circuit, and a third circuit. The first circuit generates a first clock signal. The second circuit divides the frequency of the first clock signal to generate a second clock signal. The third circuit generates a t... | 02/17/2009 |
| 7486126 | Semiconductor integrated circuit with pulse generation sections This invention provides a technique for enhancing an operating frequency and improving reliability in a system using at least level sense type sequence circuits as a plurality of sequence circuits. A microcomputer includes a clock generator configured as a clock sup... | 02/03/2009 |
| 7479819 | Clock distribution network, structure, and method for providing balanced loading in integrated circuit clock trees A clock distribution network, structure, and method for providing balanced loading is disclosed. In particular, a clock distribution network may be formed of one or more clock fanout distribution levels. Each respective distribution level may include an equal number... | 01/20/2009 |
| 7414451 | Clock generator for semiconductor memory apparatus The clock generator for semiconductor memory apparatus which includes: a first divider; a first delay unit; a second divider; a second delay unit; a duty-cycle corrector; a third divider; a third delay unit; a phase comparator; and a delay time setting unit. The clo... | 08/19/2008 |
| 7411437 | Triggering events at fractions of a clock cycle Generally, the embodiments presented are directed to circuits and methods for triggering an event at a fraction of a clock cycle. A triggering circuit can comprise two or more input circuits that output an event signal. The event signal is received by one of two or ... | 08/12/2008 |
| 7405607 | Clock generation circuit capable of setting or controlling duty ratio of clock signal and system including clock generation circuit A clock generation circuit receives a reference clock signal for outputting clock signals to peripheral circuits. A duty ratio of at least one of output buffer signals output from buffer circuits included in the clock generation circuit is varied so that a duty rati... | 07/29/2008 |
| 7403074 | Oscillator An oscillator, generating multiple phases of clock signals having a uniform phase difference with a high precision by a simple configuration, includes a plurality of NAND circuits ND1 to ND8 having the same number of input terminals connected in a ring... | 07/22/2008 |
| 7397288 | Fan out buffer and method therefor In one embodiment, a fan out buffer has the inputs of a plurality of output followers connected to the output of a plurality of distribution gates. ... | 07/08/2008 |
| 7394303 | Pulse generator using latch and control signal generator having the same An exemplary embodiment of the present invention provides a pulse generator generating a control signal to control a latch unit included in a source driver for sequentially latching input data applied to a source data line of a display device, wherein the pulse gene... | 07/01/2008 |
| 7385430 | Data output clock generating circuit and method of generating data output clock of semiconductor memory apparatus A data output clock generating circuit for a semiconductor memory apparatus includes a rising data output clock generating unit which combines a rising clock with a signal to be generated in response to a rising output enable signal and a falling clock to generate a... | 06/10/2008 |
| 7383373 | Deriving corresponding signals Apparatus used in deriving corresponding signals includes first and second circuitry. The first circuitry derives, from a source-terminated first signal driven from a Peripheral Control Interface (PCI) Express compatible source, an AC-coupled second signal. The seco... | 06/03/2008 |
| 7368953 | Buffer A buffer is disclosed. The buffer may include a buffer controller for buffering a refresh signal enabled in an auto-refresh operation synchronously with an external clock signal, a logic circuit for performing a logic operation with respect to an output signal from ... | 05/06/2008 |
| 7370134 | System and method for memory hub-based expansion bus A system memory includes a memory hub controller, a memory module accessible by the memory hub controller, and an expansion module having a processor circuit coupled to the memory module and also having access to the memory module. The memory hub controller is coupl... | 05/06/2008 |
| 7368945 | Logic circuit, timing generation circuit, display device, and portable terminal When a buffer is formed by using transistors having large element characteristic variations, the deviation of the timing between the input clock pulse and the reset pulse is likely to occur. When the deviation of the timing becomes larger, a malfunction is caused to... | 05/06/2008 |
