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| Number | Title | Issue Date |
| 7902899 | Apparatus and method of generating reference clock for DLL circuit An apparatus for generating a reference clock for a DLL circuit includes a buffering unit configured to buffer an external clock so as to generate a first reference clock and a second reference clock, and to invert the second reference clock so as to generate a nega... | 03/08/2011 |
| 7800424 | Apparatus for supplying overdriving signal An apparatus for supplying an overdriving signal in a memory apparatus. The apparatus includes: a voltage detecting block that outputs a plurality of detection signals according to the level of an external voltage, and a pulse generator that outputs the overdriving ... | 09/21/2010 |
| 7768333 | Apparatus and method of generating reference clock for DLL circuit An apparatus for generating a reference clock for a DLL circuit includes a buffering unit configured to buffer an external clock so as to generate a first reference clock and a second reference clock, and to invert the second reference clock so as to generate a nega... | 08/03/2010 |
| 7737752 | Techniques for integrated circuit clock management A clock generator (622) includes a first circuit (812) and a second circuit (814). The first circuit (812) includes a first clock input configured to receive a first clock signal at a first frequency, a second clock input configured to re... | 06/15/2010 |
| 7598790 | Clock synthesis using polyphase numerically controlled oscillator A clock synthesis circuit includes a polyphase numerically controlled oscillator, an extraction circuit, and a clock signal generation circuit. The polyphase numerically controlled oscillator generates sets of periodic output signals. Each set of the periodic output... | 10/06/2009 |
| 7573312 | Apparatus and method of controlling operation frequency in DLL circuit A frequency multiplier increases the frequency of an external clock and outputs a high-frequency external clock. A period determinator determines whether or not a predetermined period of the external clock elapses and outputs a period determination signal. A frequen... | 08/11/2009 |
| 7433392 | Wireless communications device performing block equalization based upon prior, current and/or future autocorrelation matrix estimates and related methods A wireless communications device may include a wireless receiver for receiving signals comprising alternating known and unknown symbol portions, and a demodulator connected thereto. The demodulator may include a channel estimation module for generating respective ch... | 10/07/2008 |
| 7433430 | Wireless communications device providing enhanced block equalization and related methods A wireless communications device may include a wireless receiver receiving signals having alternating known and unknown symbol portions over a channel, and a demodulator systolic array. The demodulator systolic array may include a channel estimation module generatin... | 10/07/2008 |
| 7427879 | Frequency detector utilizing pulse generator, and method thereof The present invention discloses a frequency detecting apparatus for detecting a frequency of an input clock. The frequency detecting apparatus includes: a pulse generator, a digital signal generator, and a decoder. The pulse generator is coupled to the input clock f... | 09/23/2008 |
| 7423459 | Clock signal switching device, clock signal switching method, data bus switching device, and data bus switching method A clock signal switching device includes: a plurality of signal synchronization generation means for generating mask signals and synchronized switching signals; a plurality of clock signal mask means for generating masked clock signals; a synchronized switching sign... | 09/09/2008 |
| 7403044 | Method of producing balanced data output Strobe signals are coupled to a phase detector which compares rising and falling edges of the respective strobe signals. If the phase detector determines that there is a mismatch, it outputs an UP or DOWN control signal to a control circuit. The control circuit then... | 07/22/2008 |
| 7352224 | Pulse generator and method for generating a pulse train A method for generating a pulse train is provided with adjustable start and end times of individual pulses, in which additional clock signals are generated from a 0th clock signal, the signals which in each case have a frequency of the 0th clock signal and whose pha... | 04/01/2008 |
| 7348863 | Simple time domain pulse generator A pulse generating circuit and related method, for producing extremely narrow pulses for use in monolithic microwave integrated circuits (MMICs) for radar, high-speed sampling, pulse radio and other applications. A sinusoidal input signal is supplied to two nonlinea... | 03/25/2008 |
| 7334152 | Clock switching circuit A clock switching circuit comprises: a composite clock generation circuit, which is to receive a first clock, a second clock, and a clock switching execution signal for switching between the first clock and the second clock, and to make a level of the clock fixed to... | 02/19/2008 |
| 7324559 | Centralized synchronization for wireless networks This invention synchronizes the sample clocks of an entire wireless network from a single central base station. Unlike a conventional digital radio network where every terminal must have a synchronization circuit in its receiver to adjust the sample clock, each of t... | 01/29/2008 |
| 7321244 | Clock switching device and clock switching method A clock switching device capable of automatic switching to a clock distribution system for back-up without interrupting processing of the device, which includes an abnormality detection unit which detects lack of coincidence in a logical level between a current cloc... | 01/22/2008 |
| 7301375 | Off-chip driver circuit and data output circuit using the same An off-chip driver circuit including a plurality of delay circuits, at least two of which have different delay times, in which the delay circuits receive a data signal and generate delayed data signals, respectively. The circuit also includes a plurality of off-chip... | 11/27/2007 |
| 7295055 | Device for eliminating clock signal noise in a semiconductor integrated circuit A semiconductor integrated circuit includes a integration circuit which has a first integrating portion and a second integrating portion. The semiconductor integrated circuit also includes a data input portion, data processing portion and data output portion. A cloc... | 11/13/2007 |
| 7292020 | Remote DC-DC converter for high current, low voltage applications A remote voltage regulator module (VRM) for high-current, low voltage applications. In one embodiment, an electronic system includes a VRM configured to provide a DC output voltage. The VRM is coupled to a load board via a first bus bar and a second bus bar. The VRM... | 11/06/2007 |
| 7288980 | Multiple mode clock receiver A multiple mode clock receiver including first and second input AC-coupled capacitors, first and second voltage dividers and a differential amplifier. The voltage dividers each include first and second junctions, respectively, coupled to the first and second AC-coup... | 10/30/2007 |
| 7259607 | Integrated semiconductor memory with clock generation An integrated semiconductor memory includes a clock generator circuit driven by an external clock signal and a control circuit driven by the external clock signal. The clock generator circuit generates an internal clock signal with a first level if the external cloc... | 08/21/2007 |
| 7254505 | Method and apparatus for calibrating delay lines A delay line (DL) circuit used to generate test pattern waveforms has a pulse generating circuit that is used during calibration to generate a pulse signal upon receiving a signal edge. A delay line of the DL circuit receives the pulse signal and delays the pulse si... | 08/07/2007 |
| 7245153 | Level shift circuit having timing adjustment circuit for maintaining duty ratio A level shift circuit for shifting levels of a pair of binary input signals having a first voltage range to produce a pair of binary output signals having a second voltage range includes a first circuit to shift a level of a first one of the binary input signals the... | 07/17/2007 |
| 7233187 | Dual-mode pulse generator A pulse generator electrical circuit capable of operating as both a clock-based pulse generator and a delay-based pulse generator while minimizing the limitations of these two types of pulse generators is disclosed. When the pulse generator operates in “delay mode... | 06/19/2007 |
| 7205829 | Clocked standby mode with maximum clock frequency A method and apparatus for controlling a voltage generator of a memory device are provided. In one embodiment, a first clock signal and a second clock signal are provided. The voltage generator is selectively enabled in conjunction with the first clock signal when a... | 04/17/2007 |
| 7203611 | Timing generator, test apparatus and skew adjusting method There is provided a timing generator generating a timing signal of a predetermined period. The timing generator includes a set/reset latch, a set unit supplying the set signal, and a reset unit supplying the reset signal, in which the set unit includes: a first vari... | 04/10/2007 |
| 7173470 | Clock sources and methods with reduced clock jitter Clock sources are provided which are especially useful for reducing phase noise in signal samplers that typically provide samples of an analog input signal in signal-conditioning systems such as analog-to-digital converters. This phase noise reduction is realized wi... | 02/06/2007 |
| 7173495 | Redundant back-up PLL oscillator phase-locked to primary oscillator with fail-over to back-up oscillator without a third oscillator A redundant-source clock generator has only two oscillators, rather than three oscillators. A secondary oscillator is phase-locked to a primary clock from a primary oscillator using a phase detector, charge pump, and filter that generate a control voltage to the sec... | 02/06/2007 |
| 7157952 | Systems and methods for implementing delay line circuitry Memory devices used to control delay line circuitry, and that may be implemented in one embodiment to provide a self-tuning delay line device using empirical calibration technique/s to achieve a desired signal delay. The memory control device may be implemented to s... | 01/02/2007 |
| 7145368 | Clock signal switching device, clock signal switching method, data bus switching device, and data bus switching method A clock signal switching device includes: a plurality of signal synchronization generation means for generating mask signals and synchronized switching signals; a plurality of clock signal mask means for generating masked clock signals; a synchronized switching sign... | 12/05/2006 |
| 7106119 | Circuit for the temporary interruption of a sync signal A stop and release circuit of a sync signal, to temporarily suspend or interrupt the sync signal, the input sync signal having a plurality of leading edges and a plurality of trailing edges, the circuit including a first divider that receives the input sync signal a... | 09/12/2006 |
| 7098123 | Methods of forming a semiconductor device having a metal gate electrode and associated devices Methods of forming a semiconductor device having a metal gate electrode include sequentially forming a gate insulator, a gate polysilicon layer and a metal-gate layer on a semiconductor substrate. The metal-gate layer and the gate polysilicon layer are sequentially ... | 08/29/2006 |
| 7084685 | Method and related apparatus for outputting clock through a data path An output clock is provided by a logic module and at least one flip-flop based on a reference clock. Each flip-flop receives the reference clock at a corresponding clock end and changes a signal level outputted at a corresponding output port according to rising or f... | 08/01/2006 |
| 7075352 | Latch-based pulse generator There is provided a pulse generator capable of generating a pulse with a reduced number of transistors that toggle in response to a clock signal, thereby reducing power consumption. The pulse generator includes a plurality of unit cells, wherein an nth unit cell (n ... | 07/11/2006 |
| 7057436 | Clock circuit for a microprocessor A clock circuit comprises an analog clock element, a digital clock element, and a controller. The analog clock element is configured to generate an oscillating output. The digital clock element is configured to generate a digital clock output. The controller is conf... | 06/06/2006 |
| 7042267 | Gated clock circuit with a substantially increased control signal delay A gated clock circuit outputs a gated clock signal in response to a master clock signal and a control signal that has a rising or falling edge that follows a rising edge of the master clock signal by a delay. The gated clock signal has a pulse width that is equal to... | 05/09/2006 |
| 6980748 | SiGe or germanium flip chip optical receiver A synchronized optical clocking signal is provided to a plurality of optical receivers by providing a layer of a high absorption coefficient material, such as SiGe or Ge, on a front surface of a low absorption coefficient substrate, such as silicon. Diodes are forme... | 12/27/2005 |
| 6972607 | Clock signal regeneration circuitry A method and circuit for regenerating clock signals. The method and circuit convert clock signals having either single- ended clock pulses or differential clock pulses into clock signals having substantially the same voltage swing. In one embodiment, the single-ende... | 12/06/2005 |
| 6927639 | Method and apparatus for generating high frequency signals by a plurality of low frequency signals with multiple phases Method and related apparatus for realizing frequency-multiplication by generating a high frequency signal according to a plurality of low frequency signals. The method includes: according to a plurality output signals generated by a phase-locked loop (PLL) or a dela... | 08/09/2005 |
| 6924686 | Synchronous mirror delay (SMD) circuit and method including a counter and reduced size bi-directional delay line A synchronous mirror delay (SMD)includes a model delay line that is coupled to a bi-directional delay line. In operation, an initial edge an input clock signal is applied through the model delay line to the bi-directional delay line. The SMD thereafter operates in a... | 08/02/2005 |
