Did You Know...
...Chester Carlson was a patent agent who tired of having to make multiple copies of patent applications using the only duplication method available at the time: carbon paper. In 1959 he came up with a new copying system and took it to IBM for evaluation. The "experts" at IBM determined potential sales to be only 5,000 units because people wouldn't want to use a bulky machine when they had carbon paper. Carlson's invention was the xerography process, the company founded on the system is Xerox.
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| Number | Title | Issue Date |
| 8143932 | Grid clock distribution network reducing clock skew and method for reducing the same A clock distribution network includes a plurality of clock drivers for outputting clock signals. At least one of the plurality of clock drivers has a driving capacity that is not equal to a driving capacity of at least another one of the plurality of clock drivers. ... | 03/27/2012 |
| 8138812 | Device for generating clock in semiconductor integrated circuit Various embodiments of a semiconductor integrated circuit. According to one exemplary embodiment, a semiconductor integrated circuit includes a multi-phase clock generator that is configured to generate a multi-phase internal clock; a first edge combining unit that ... | 03/20/2012 |
| 7956664 | Clock distribution network architecture with clock skew management Disclosed herein is a digital system that includes a distribution network having a path to carry a reference clock and an adjustable delay element disposed along the path, and first and second clock domains coupled to the distribution network to receive the referenc... | 06/07/2011 |
| 7760000 | Clock generator A multiphase clock with high resolution is generated. A first clock generator circuit (120) includes n level converters BUFs that conduct level conversion on two input signals, and generate a pair of pulse signals that switch the levels with reference to a cr... | 07/20/2010 |
| 7679416 | High speed clock distribution transmission line network The invention is directed to a method for clock distribution and VLSI circuits include a clock distribution network. In a method of the invention, a transmission lines are patterned as to connect a clock tree and a periodic waveform clock, preferably a sine waveform... | 03/16/2010 |
| 7528642 | Semiconductor integrated circuit device and method of outputting signals on semiconductor integrated circuit A semiconductor integrated circuit device includes a semiconductor substrate having a first area. A first counter is provided in the first area, cyclically counts and outputs a first counter signal as a result of counting. A global reset circuit is provided on the s... | 05/05/2009 |
| 7474137 | Integrated circuit clock distribution A circuit is provided with a plurality of interconnected logic blocks, a main clock generator for distributing a reference clock signal to the logic blocks. Each logic block in the circuit comprises a local clock generator that generates a set of synchronized local ... | 01/06/2009 |
| 7446587 | Semiconductor device and driving method thereof The invention provides a semiconductor device which can suppress a variation of clock signals. According to the invention, a single clock signal is divided into a plurality of clock signals and supplied to each of a plurality of circuits in a semiconductor device. P... | 11/04/2008 |
| 7443221 | System and method for fully digital clock divider with non-integer divisor support A system and method that use a first clock to digitally generate a second clock, wherein the ratio of the frequency of the first clock to the frequency of the second clock is a non-integer. Circuitry may be used to ensure that the first clock, or input clock, has a ... | 10/28/2008 |
| 7427879 | Frequency detector utilizing pulse generator, and method thereof The present invention discloses a frequency detecting apparatus for detecting a frequency of an input clock. The frequency detecting apparatus includes: a pulse generator, a digital signal generator, and a decoder. The pulse generator is coupled to the input clock f... | 09/23/2008 |
| 7423470 | Pulse generator A split signal pulse generator (“SSPG”) that generates a difference signal from two split signals from a splitter module, where one of the split signals may be time delayed by a delay module, where the delay module may be a transmission line having a time delay ... | 09/09/2008 |
| 7403058 | Test clock generating apparatus A test clock generating apparatus is provided in the invention. The test clock generating apparatus includes an at-speed clock generator and a multiplexer. The at-speed clock generator is for receiving a reference clock signal and a scan chain enable signal and outp... | 07/22/2008 |
| 7382171 | Semiconductor circuit for detecting a signal propagation time There is provided a semiconductor circuit including three or more nodes at least including one input node and one output node, plural paths which are connected between the three or more nodes and whose signal propagation directions between the nodes are regulated, a... | 06/03/2008 |
| 7373616 | Designing apparatus, and inspection apparatus for designing an integrated circuit having reduced leakage current A method of designing a semiconductor integrated circuit, comprises: replacing a circuit element disposed in the semiconductor integrated circuit with a transistor having a high threshold value or a circuit element having a small juxtaposition number in order to pre... | 05/13/2008 |
| 7360108 | Multi-link receiver and method for processing multiple data streams A multi-link receiving mechanism (MRM) is disclosed comprising a plurality of receivers. Each receiver receives a separate data stream, and all receivers receive the same clock signal. The data streams may arrive at the MRM out of alignment relative to each other (i... | 04/15/2008 |
| 7348837 | Point diffusion signal distribution with minimized power consumption and signal skew For distributing a signal to loads in an area, the area is divided into a plurality of regions. A respective signal point is disposed in each region for providing the signal to a load in the region. A respective diffusion point is disposed between any two neighborin... | 03/25/2008 |
| 7348863 | Simple time domain pulse generator A pulse generating circuit and related method, for producing extremely narrow pulses for use in monolithic microwave integrated circuits (MMICs) for radar, high-speed sampling, pulse radio and other applications. A sinusoidal input signal is supplied to two nonlinea... | 03/25/2008 |
| 7339412 | Digital clock generator The invention relates to a clock generator comprised of a system clock input (2) for applying a high-frequency system clock signal, of a digital input (3) for applying a settable digital increment value, of an adder (6) for adding the increment ... | 03/04/2008 |
| 7336115 | Redundancy in signal distribution trees A signal distribution tree structure for distributing signals within a plurality of signal tree branches to a plurality of signal sinks, wherein the signal in subsequent sub trees (11) is driven by a preceding amplifier (2), which is characterized in t... | 02/26/2008 |
| 7336116 | Clock supply circuit The clock supply circuit of the present invention comprises a plurality of clock supply paths and a clock gate circuit. The clock supply paths branch a clock signal and supply each of the branched clock signals to a plurality of sequential circuits via a buffer. The... | 02/26/2008 |
| 7334209 | Method and system for generating multiple implementation views of an IC design A method and system for generating from a high-level placement specification the layout and schematic implementation data is disclosed. In addition packaging data and a software model may also be generated. In one embodiment an array of rows and columns is formed on... | 02/19/2008 |
| 7327180 | Information processing apparatus with adjustable system clock An information processing apparatus is constructed by a system PLL, a first unit, a second unit, and a system board on which they are mounted. A delay setting circuit in which a variation and delay elements (a gate delay and a line delay) which are equivalent to tho... | 02/05/2008 |
| 7324403 | Latency normalization by balancing early and late clocks A method, apparatus, and system are disclosed. In one embodiment the method comprises inputting an early clock signal and a late clock signal to a memory device and generating an average clock signal for the memory device by averaging the early clock signal and the ... | 01/29/2008 |
| 7317343 | Pulse-generation circuit with multi-delay block and set-reset latches In one embodiment of the invention, a pulse-generation circuit for generating control signals has clock-delay circuitry for generating a plurality of differently delayed clock signals. Each control signal is generated by a set-reset latch that receives its set and r... | 01/08/2008 |
| 7317342 | Clock distribution network using feedback for skew compensation and jitter filtering A clock distribution network for clock distribution in an integrated circuit (IC) using digital feedback for skew compensation and jitter filtering. In an embodiment, a number of clock processor nodes are distributed throughout the clock distribution network on the ... | 01/08/2008 |
| 7312487 | Three dimensional integrated circuit A three dimensional (3D) integrated circuit (IC), 3D IC chip and method of fabricating a 3D IC chip. The chip includes multiple layers of circuits, e.g., silicon insulator (SOI) CMOS IC layers, each including circuit elements. The layers may be formed in parallel an... | 12/25/2007 |
| 7310007 | Logic circuit, system for reducing a clock skew, and method for reducing a clock skew A logic circuit includes a first flip-flop configured to include a first input terminal introducing a clock, a first output terminal supplying the clock and a first internal wiring connecting the first input terminal and the first output terminal, and a second flip-... | 12/18/2007 |
| 7310011 | Clock signal adjuster circuit The present invention relates to a clock signal distribution circuit for distributing the clock signal to circuits such as LSI integrated circuits, and, more specifically, provides a clock adjuster circuit, which performs phase difference adjustment of clock signals... | 12/18/2007 |
| 7304516 | Method and apparatus for digital phase generation for high frequency clock applications An apparatus and method for generating phase-related clocks are disclosed. A clock input is delayed by an alignment magnitude to generate a first phase signal. The first phase signal is delayed by the phase alignment magnitude to generate a first phase delay signal.... | 12/04/2007 |
| 7304522 | Spread spectrum clock generator A spread spectrum clock generator includes a plurality of delay cells, wherein each delay cell includes at least one delayer receiving an external clock signal and causing a predetermined propagation delay to the received clock signal, and a controller transmitting ... | 12/04/2007 |
| 7301385 | Methods and apparatus for managing clock skew An apparatus is disclosed which includes a signal generator providing a first signal having a first frequency; a clock tree operative to propagate the first signal to at least one clock mesh of the apparatus; and a final buffer operative to receive the first signal,... | 11/27/2007 |
| 7301384 | Multimode, uniform-latency clock generation circuit A multimode, uniform-latency clock generation circuit (CGC) is described herein. In one example, the multimode, uniform-latency CGC generates a pulse clock signal via a clock generation path responsive to a clock chopping signal being active and generates a phase cl... | 11/27/2007 |
| 7296104 | Automated calibration of I/O over a multi-variable eye window A method and apparatus for automated calibration of I/O over a multi-variable eye window is provided. A transmitter may conduct data transmissions to a receiver of an integrated circuit (IC) over a plurality of signal lines. The data transmissions may be conducted a... | 11/13/2007 |
| 7296173 | Semiconductor integrated circuit A semiconductor integrated circuit is provided in which the timing margin for fetching data is prevented from being reduced even in the case where the duty ratio of a clock signal is different from 50%. The semiconductor integrated circuit includes: a clock input te... | 11/13/2007 |
| 7282966 | Frequency management apparatus, systems, and methods Apparatus and systems, as well as methods and articles, may operate to select a microprocessor clock frequency responsive to a desired voltage and/or a desired temperature of operation. ... | 10/16/2007 |
| 7278120 | Methods and apparatuses for transient analyses of circuits Methods and apparatuses for transient analyses of a circuit using a hierarchical approach. In one embodiment, the cells are grouped locally on the power supply network according to average power dissipation. A time varying current of each cell group is estimated usi... | 10/02/2007 |
| 7272526 | Method and apparatus for autocalibrating a plurality of phase-delayed clock signal edges within a reference clock period An apparatus for measuring the time delay between adjacent clock edges includes target and delay signal paths, a variable delay module in said delay signal path, the delay cell having a delay bias input, and a phase detector having respective inputs coupled to the t... | 09/18/2007 |
| 7263567 | Method and apparatus for lowering the die temperature of a microprocessor and maintaining the temperature below the die burn out According to one embodiment, a method is disclosed. The method includes determining whether the temperature of a central processing unit (CPU) exceeds a predetermined threshold. In addition, the method includes generating a first interrupt if the temperature of the ... | 08/28/2007 |
| 7259608 | System and method for open-loop synthesis of output clock signals having a selected phase relative to an input clock signal Delay circuits are used in a manner similar to a synchronized mirror delay circuit to generate a quadrature clock signal from an input clock signal. The input clock signal is coupled through a series of first delay circuit for one-half the period of the input clock ... | 08/21/2007 |
| 7240315 | Automated local clock placement for FPGA designs A method (500) of placing local clock nets in a circuit design can include identifying the local clock nets for the circuit design and selecting components corresponding to each local clock net (510,515), and assigning initial locations to each compone... | 07/03/2007 |
