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| Number | Title | Issue Date |
| 7804348 | Clock data recovery with high speed level shift Clock data recovery circuitry with a high speed level shifting circuits and methods are disclosed. One embodiment provides clock data recover with a high speed level shifting circuit that uses an input signal to generate two intermediate signals and uses the interme... | 09/28/2010 |
| 7746143 | Clock generating circuit and semiconductor device provided with clock generating circuit An object is to provide a clock generating circuit that can suppress variation of an oscillation frequency from the clock generating circuit, which is due to a change in the output voltage according to a discharging characteristic of the battery, and effectively uti... | 06/29/2010 |
| 7737751 | Periphery clock distribution network for a programmable logic device A programmable logic device (PLD) includes a signal distribution network, separate from the high-quality, low-skew clock distribution networks of the PLD, for distributing, from peripheral input/output regions of the PLD, clock-type signals. The signal distribution ... | 06/15/2010 |
| 7683691 | Clock supplying apparatus Disclosed herein is a clock supplying apparatus for supplying a clock to a digital circuit, including: a differential clock driver; a first clock line along which a first clock of a positive phase from the clock driver propagates; a second clock line along which a s... | 03/23/2010 |
| 7659763 | Conditioning input buffer for clock interpolation A conditioning buffer is provided for a clock interpolator that controls the duration of the clock edges to achieve high-linearity interpolation. The conditioning buffer includes a first buffer and a second buffer, with a fixed or variable strength, that receive the... | 02/09/2010 |
| 7656215 | Clock generator circuit, clock selector circuit, and semiconductor integrated circuit A clock generator circuit provides an output clock without an abnormal waveform pulse which causes faulty operation in other function circuits. A phase synchronizing circuit outputs a second clock synchronized with a first clock. A selector signal generator circuit ... | 02/02/2010 |
| 7429883 | Oscillator configured to complete an output pulse after inactivation An oscillator includes an oscillating block for generating a control signal in response to an enable signal, wherein the control signal is periodically toggled and a feedback block for receiving the control signal to generate the enable signal in response to an osci... | 09/30/2008 |
| 7414451 | Clock generator for semiconductor memory apparatus The clock generator for semiconductor memory apparatus which includes: a first divider; a first delay unit; a second divider; a second delay unit; a duty-cycle corrector; a third divider; a third delay unit; a phase comparator; and a delay time setting unit. The clo... | 08/19/2008 |
| 7406615 | Control unit for generating a clock pulse as a function of output signals outputted from at least two clock outputs A control unit featuring clocked data transmission between a processor and at least one further circuit, the processor itself outputting the clock pulse. The processor monitors the clock pulse based on the output signals of at least two clock outputs. ... | 07/29/2008 |
| 7403044 | Method of producing balanced data output Strobe signals are coupled to a phase detector which compares rising and falling edges of the respective strobe signals. If the phase detector determines that there is a mismatch, it outputs an UP or DOWN control signal to a control circuit. The control circuit then... | 07/22/2008 |
| 7378894 | Method and system for clock routing and compensation A method, apparatus, article of manufacture, and system, the method including, in some embodiments, providing a differential clock ganging structure to receive complementary differential clock signals, the differential clock ganging structure outputting clock gangin... | 05/27/2008 |
| 7369453 | Multi-port memory device and method of controlling the same A multi-port memory device providing various frequencies for ports is disclosed. The multi-port memory device includes a memory core, a clock generator and a plurality of ports. The clock generator generates an internal clock signal based on an external clock signal... | 05/06/2008 |
| 7366271 | Clock and data recovery device coping with variable data rates A clock and data recovery (CDR) device is disclosed that is capable of recovering a clock signal from a data signal that has a variable data rate. The CDR device includes a reference clock generating section for dividing a basic clock by a first predetermined value ... | 04/29/2008 |
| 7362107 | Systems and methods for automatically eliminating imbalance between signals A calibrating system for automatically eliminating or reducing imbalance between a first signal and a second signal is disclosed. The calibrating system includes: a programmable delay module, receiving to the first and the second signals; a phase detecting module, c... | 04/22/2008 |
| 7362134 | Circuit and method for latch bypass A device includes a first combinatorial logic stage having a first input to receive a first data value, a second input to receive a bypass value and an output to provide one of a representation of the first data value or a first predetermined value based on the bypa... | 04/22/2008 |
| 7356076 | System and method supporting auto-recovery in a transceiver system A method and apparatus are disclosed to aid a transceiver chip, in a serial data communications system, in recovering from a system-side, out-bound data clocking problem. If a problem with a primary clock signal, used to clock data from a system-side of a transceive... | 04/08/2008 |
| 7356785 | Optimizing IC clock structures by minimizing clock uncertainty A process is provided for optimizing a clock net in the form of a tree having a root defined by a driver pin and a plurality of leaves defined by driven pins. The process includes forcing a first buffer to a center of gravity of the plurality of leaves, inserting a ... | 04/08/2008 |
| 7353420 | Circuit and method for generating programmable clock signals with minimum skew A programmable clock deskewer generates an output clock with minimal clock skew. This is accomplished by means of a single series path coupling the input clock to the output clock. The programmable clock deskewer includes: an output clock generator, responsive to th... | 04/01/2008 |
| 7352222 | Clock generator with programmable non-overlapping-clock-edge capability A system and method for generating and optimizing clock signals with non-overlapping edges on a chip using a unique programmable on-chip clock generator. Overlapping of the edges of the clocking signals is avoided by adjusting an amount of delay introduced in the on... | 04/01/2008 |
| 7348821 | Programmable high-resolution timing jitter injectors high-resolution timing jitter injectors A device includes a first circuit having rows and columns of delay cells to generate delayed signals based on an input signal. The delayed signals are selectable and have a different delay from one another with respect to the input signal. The device is programmable... | 03/25/2008 |
| 7350116 | Clock synchronization and fault protection for a telecommunications device According to one embodiment, a telecommunications device includes a bus and a controller coupled to the bus that generates a system clock signal according to a first reference clock signal and communicates the system clock signal using the bus. The controller detect... | 03/25/2008 |
| 7342404 | Device for measurement and analysis of electrical signals of an integrated circuit component According to the invention, one or more external test connection contact points (pads; pins; balls), are provided in an integrated circuit component (chip) (1), through which signals (4, 5, 6) that are to be measured or analyzed are selectively fed, e.... | 03/11/2008 |
| 7337294 | Method and apparatus for adjusting the performance of a synchronous memory system A method and apparatus for adjusting the performance of a memory system is provided. A memory system comprises a master device and a slave device. A memory channel couples the master device to the slave device such that the slave device receives the system operating... | 02/26/2008 |
| 7333527 | EMI reduction using tunable delay lines The clock signal is the dominant source of electromagnetic interference (EMI) for many digital electronic devices. EMI generated by these electronic devices must be suppressed to avoid interference with other electronic devices and to satisfy FCC regulations. The pr... | 02/19/2008 |
| 7325058 | Method and system for controlling subscriber access in a network capable of establishing connections with a plurality of domain sites A method for controlling subscriber access in a network capable of establishing connections with a plurality of domains includes receiving a communication from a subscriber using a first communication network coupled to at least one other communication network, the ... | 01/29/2008 |
| 7321244 | Clock switching device and clock switching method A clock switching device capable of automatic switching to a clock distribution system for back-up without interrupting processing of the device, which includes an abnormality detection unit which detects lack of coincidence in a logical level between a current cloc... | 01/22/2008 |
| 7319354 | Signal processing apparatus having internal clock signal source A signal processing apparatus includes: (a) A signal treating unit for effecting signal treating functions to present a treated signal at an output. (b) A clock generator receiving a clock signal and using the clock signal for presenting an internal clock signal for... | 01/15/2008 |
| 7319634 | Address converter semiconductor device and semiconductor memory device having the same An address converter of a semiconductor device comprises a clock generating portion for generating at least one clock signal when a power voltage is applied; a control signal setting means for setting a control signal during a mode setting operation; a polarity sele... | 01/15/2008 |
| 7310026 | Semiconductor integrated circuit with function to detect state of stable oscillation A semiconductor integrated circuit includes a reference-voltage circuit configured to produce a predetermined reference voltage at an output node thereof, a comparator, coupled to a node to which an oscillating signal is supplied and to the output node of the refere... | 12/18/2007 |
| 7310011 | Clock signal adjuster circuit The present invention relates to a clock signal distribution circuit for distributing the clock signal to circuits such as LSI integrated circuits, and, more specifically, provides a clock adjuster circuit, which performs phase difference adjustment of clock signals... | 12/18/2007 |
| 7301385 | Methods and apparatus for managing clock skew An apparatus is disclosed which includes a signal generator providing a first signal having a first frequency; a clock tree operative to propagate the first signal to at least one clock mesh of the apparatus; and a final buffer operative to receive the first signal,... | 11/27/2007 |
| 7298186 | Control circuit for command signals of clock generator A control circuit for command signals of a clock generator includes a power supply end, an output end, a control end, a diode, a first resistor and a second resistor. The first resistor, the diode, and the second resistor are connected in series between the power su... | 11/20/2007 |
| 7296170 | Clock controller with clock source fail-safe logic A microcontroller integrated circuit with a clock controller and a processor automatically switches the source of the clock signal that clocks the processor from a failed fast external precision oscillator to a slow internal backup oscillator, then enables a fast in... | 11/13/2007 |
| 7279996 | Method of functionality testing for a ring oscillator A method and apparatus is provided for testing the logic functionality and electrical continuity of a ring oscillator comprising an odd number of inverters connected to form a closed loop. In the method and apparatus, a known value is forced through the ring oscilla... | 10/09/2007 |
| 7276961 | Constant voltage outputting circuit A constant voltage outputting circuit has a differential amplification circuit having two inputs and an output that is connected to a gate of an output transistor. The output transistor is connected between a power supply voltage and an output terminal and controls ... | 10/02/2007 |
| 7276943 | Highly configurable PLL architecture for programmable logic A programmable logic device includes configurable phase-locked loop (PLL) circuitry that outputs multiple clock signals having programmable phases and frequencies. Each output signal is programmably selectable for use as an external clock, internal global clock, int... | 10/02/2007 |
| 7269803 | System and method for mapping logical components to physical locations in an integrated circuit design environment A system and method for mapping Intellectual Property (IP) components onto a pre-fabricated chip slice allows a user to select a target location for placement of an IP component onto a slice. A slice definition of the pre-fabricated chip slice is searched for a lega... | 09/11/2007 |
| 7265638 | Ring oscillator circuit A ring oscillator circuit includes a ring of cascade-coupled delay stages and is controlled by a plurality of multiplexers. A feedback circuit has an input terminal coupled to an output terminal of the ring oscillator circuit. The ring oscillator circuit receives a ... | 09/04/2007 |
| 7254203 | Method and apparatus for use of high sampling frequency A/D converters for low frequency sampling A method and apparatus for adding fill-in clock pulses to an analog to digital converters input clock signal between requests for analog data acquisition. The circuit that provides the fill-in clock pulses is able to detect a request for analog data acquisition, syn... | 08/07/2007 |
| 7239167 | Utilizing clock shield as defect monitor Disclosed is a shielded clock tree that has one or more clock signal buffers and clock signal splitters, with clock signal wiring connecting the clock signal buffers to the clock signal splitters. Shielding is adjacent the clock signal wiring, where ground wiring co... | 07/03/2007 |
