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| Number | Title | Issue Date |
| 7956663 | Delay circuit, semiconductor control circuit, display device, and electronic device Disclosed herein is a delay circuit for performing one of a charge and a discharge in two stages, and delaying a signal, the delay circuit including an output section configured to output a delayed signal; two power supplies; and a delay inverter; wherein the delay ... | 06/07/2011 |
| 7932767 | Increasing charge capacity of charge transfer circuits without altering their charge transfer characteristics A technique for increasing the charge storage capacity of a charge storage device without changing its inherent charge transfer function. The technique may be used to implement a charge domain signal processing circuits such as Analog to Digital Converters (ADCs) us... | 04/26/2011 |
| RE42250 | Delay circuit and method A reduced area delay circuit and method are disclosed. The delay circuit uses a constant current source and a constant current drain to charge and discharge a capacitor and thus control the delay time of the delay circuit. The constant current source and drain can b... | 03/29/2011 |
| 7486125 | Delay cells and delay line circuits having the same Delay line circuits include a plurality of delay cells connected in series. The delay cells respectively include a first to a third logic gate. The first logic gate, in response to a selection signal, generates a first signal based on an input signal. The second log... | 02/03/2009 |
| 7408394 | Measure control delay and method having latching circuit integral with delay circuit A measure control delay includes a measuring delay line and a signal generating delay line, each of which include a plurality of series-connected delay units. A digital signal is applied to an initial delay unit in the measuring delay line and it sequentially propag... | 08/05/2008 |
| 7362155 | Method and apparatus for generating delays One embodiment pertains generally to a method of delaying based on a single clock signal. The method includes providing a first clock signal and generating a second clock signal based on the first clock signal and a third clock signal that is the inverse of the seco... | 04/22/2008 |
| 7295055 | Device for eliminating clock signal noise in a semiconductor integrated circuit A semiconductor integrated circuit includes a integration circuit which has a first integrating portion and a second integrating portion. The semiconductor integrated circuit also includes a data input portion, data processing portion and data output portion. A cloc... | 11/13/2007 |
| 7288978 | Delay circuit and ring oscillator using the same In a delay circuit, when a first conductivity-type transistor (M6) becomes conductive on the basis of one level of its input signal, a first current path is formed through a source side transistor (M4), the first conductivity-type transistor (M6... | 10/30/2007 |
| 7274237 | Measure control delay and method having latching circuit integral with delay circuit A measure control delay includes a measuring delay line and a signal generating delay line, each of which include a plurality of series-connected delay units. A digital signal is applied to an initial delay unit in the measuring delay line and it sequentially propag... | 09/25/2007 |
| 7274223 | Semiconductor device As devices are often different in the characteristics from one another, semiconductor chips based on the devices have discrepancies in the performance. A semiconductor device having a semiconductor switching element and a drive controlling means (1) for gener... | 09/25/2007 |
| 7239185 | Driver circuit connected to pulse shaping circuitry An integrated circuit driver includes an output stage having source drain paths of a PFET and NFET connected in series with each other across DC power supply terminals. A pair of inverters simultaneously responsive to a bilevel signal drive gate electrodes of the PF... | 07/03/2007 |
| 7167035 | Delay circuitry and method therefor One use for delay adjustment circuit (32), coarse-grain delay offset circuit (34), and fine-grain delay synthesis circuit (36) may be as part of a delay replication circuit (30) used to replicate the frequency versus voltage behavior of a... | 01/23/2007 |
| 7132868 | Semiconductor device As devices are often different in the characteristics from one another, semiconductor chips based on the devices have discrepancies in the performance. A semiconductor device having a semiconductor switching element and a drive controlling means (1) for gener... | 11/07/2006 |
| 7102407 | Programmable clock delay circuit A delay circuit. The delay circuit includes a first circuit, a falling edge delay circuit and a rising edge delay circuit. The first circuit includes a circuit input for receiving a reference signal and a circuit output for outputting a delayed signal. The falling e... | 09/05/2006 |
| 7057450 | Noise filter for an integrated circuit A noise filter for an integrated circuit is proposed. The noise filter comprises a CMOS inverter and two capacitors. The input of the CMOS inverter is coupled with an input pad of the integrated circuit and the output of the CMOS inverter is coupled with an input bu... | 06/06/2006 |
| 7038519 | Digital clock manager having cascade voltage switch logic clock paths A digital clock manager having differential clock signal paths is provided. The differential clock signal paths are provided by replacing single-ended circuit elements of a conventional digital clock manager with symmetrical cascade voltage switch logic (CVSL) circu... | 05/02/2006 |
| 7030668 | Voltage detector A voltage detector circuit such as a power up and/or brownout detector circuit (100) includes a comparator (102) having at least one of its inputs (104) coupled to a diode-connected transistor (108). The other input can include another di... | 04/18/2006 |
| 7019576 | Delay circuit that scales with clock cycle time A circuit having a process, voltage, and temperature (PVT) invariant delay element is disclosed. In one embodiment, the present invention includes a first and second operational transconductance amplifier (OTA), a first and second switched capacitor driven by a cloc... | 03/28/2006 |
| 7019986 | Power conversion apparatus and dead time generator A small-sized, highly efficient power conversion apparatus is provided which is capable of stabilizing its output and which can be easily applied to parallel driving. The power conversion apparatus turns on and off paired switching elements, lets an alternating curr... | 03/28/2006 |
| 7012459 | Method and apparatus for regulating heat in an asynchronous system One embodiment of the present invention provides a system that regulates heat within an asynchronous circuit. During operation, the system monitors a temperature within the asynchronous circuit. If the temperature exceeds a threshold value, the system introduces a d... | 03/14/2006 |
| 6914467 | Dual edge programmable delay unit A method and device program a dual edge programmable delay unit, that responds to an input signal with a rise time and a fall time, includes a buffer which receives the input signal and provides an output signal with programmed variable delays between the rise and f... | 07/05/2005 |
| 6911856 | Delay matching for clock distribution in a logic circuit Techniques for compensating for propagation delay differences between signals distributed within a logic circuit. A delay matching circuit mimics the internal clock-to-Q delay produced by a flop. The delay matching circuit is placed in the propagation path of an ori... | 06/28/2005 |
| 6900683 | Apparatus and method for generating a predetermined time delay in a semiconductor circuit A semiconductor arrangement is provided for generating a predetermined time delay. Two clocks are connected to two parallel, redundant semi-conductor circuits emitting clock signals from multiplexers. The redundant circuits receive delayed clock signals from one of ... | 05/31/2005 |
| 6885231 | Variable delay element for use in delay tuning of integrated circuits A method and apparatus for delay tuning an integrated circuit which includes a delay element that includes a plurality of delay stages interconnected in a cascaded relationship, each stage imposing an incremental delay upon the input signal when enabled, the delay e... | 04/26/2005 |
| 6798298 | Balancing circuit, method of operation thereof and a charge pump employing the same A balancing circuit and method of operation thereof for use with a circuit having first and second complementary drivers exhibiting different current gain characteristics. In one embodiment, the balancing circuit includes a sensing subcircuit that provides a correct... | 09/28/2004 |
| 6788126 | Semiconductor buffer circuit with a transition delay circuit A transition delay circuit having an input terminal and an output terminal is disclosed. According to one embodiment, the transition delay circuit also includes a first MOS capacitor, a second MOS capacitor, and a delay circuit. The first MOS capacitor includes a fi... | 09/07/2004 |
| 6686788 | Delay circuit of clock synchronization device using delay cells having wide delay range A delay circuit of a clock synchronization device that includes an operational amplifier for setting the level of a current control voltage according to a voltage difference between a regulation voltage and a reference voltage. A number of unit delay cell... | 02/03/2004 |
| 6628157 | Variable delay element for use in delay tuning of integrated circuits A method and apparatus for delay tuning an integrated circuit which includes a delay element that includes a plurality of delay stages interconnected in a cascaded relationship, each stage imposing an incremental delay upon the input signal when enabled, ... | 09/30/2003 |
| 6624680 | Reduction of propagation delay dependence on supply voltage in a digital circuit In one embodiment, a digital circuit element has a propagation delay that is substantially constant over a range of supply voltages applied to the digital circuit element. In another embodiment, a digital circuit element may include an input node, an outp... | 09/23/2003 |
| 6549051 | Synchronous delay generator A method for generating a variable delay of a signal, including: providing a clock indicating a sequence of sample times at regular intervals and receiving a sequence of input samples representing input values of the signal at respective sample times indi... | 04/15/2003 |
| 6525583 | Circuit configuration for enhancing performance characteristics of fabricated devices A compensation circuit includes at least one of an n-channel device connected to oppose a high-to-low transition and a p-channel device connected to oppose a low-to high transition. The n-channel and p-channel devices may be diodes, transistors, or transi... | 02/25/2003 |
| 6515529 | Semiconductor buffer circuit with a transition delay circuit The present invention is directed to a transition delay circuit. The transition delay circuit includes a delay circuit which is responsive to an input signal. The transition delay circuit produces an output signal at a common node. The transition delay ci... | 02/04/2003 |
| 6492847 | Digital driver circuit A digital driver circuit with one or more CMOS inverters intended as input stages, whereby for the MOS FETs of the inverters the channel width/length (W/L) ratio increases from stage to stage. The digital driver circuit includes an intermediate stage with... | 12/10/2002 |
| 6456137 | Semiconductor circuit, delay adjustment method therefor and layout method therefor First and second wires are disposed adjacent to each other. Even pairs of buffers and inverters are disposed on the wires. A buffer and an inverter in each of the pairs are disposed on the first or second wires respectively. The first and second wires are... | 09/24/2002 |
| 6448833 | Delay circuit A delay circuit using MOS transistors for use of load capacitance which produces a stable delay effect for variations in signal voltage is provided. A gate of a P-type MOS transistor for load capacitance and a gate of an N-type MOS transistor for load cap... | 09/10/2002 |
| 6434061 | Circuit configuration for enhancing performance characteristics of fabricated devices A compensation circuit includes at least one of an n-channel device connected to oppose a high-to-low transition and a p-channel device connected to oppose a low-to high transition. The n-channel and p-channel devices may be diodes, transistors, or transi... | 08/13/2002 |
| 6388491 | Delay circuit A delay circuit includes a capacitor, a charging/discharging control circuit receptive of an input signal for controlling at least one of the charging and the discharging of the capacitor to set a delay time in accordance with a capacitance value of the c... | 05/14/2002 |
| 6359488 | Clock buffer circuit, and interface and synchronous type semiconductor memory device with clock buffer circuit There is provided a semiconductor integrated circuit including a clock buffer capable of suppressing the increase of its chip size and decreasing its electric power consumption even if the capacity increases or even if the functional operations are varied... | 03/19/2002 |
| 6351169 | Internal clock signal generating circuit permitting rapid phase lock An internal clock signal generating circuit according to the present invention has a minute delay stage that can change a delay amount minutely and a delay stage that changes its delay amount by a larger amount. The minute delay stage responds to a contro... | 02/26/2002 |
| 6320438 | Duty-cycle correction driver with dual-filter feedback loop A clock generator has a duty cycle correction circuit that adjusts the duty cycle to 50%. A modulator is an inverter with extra source-limiting transistors in series to the power and ground supplies. A control voltage of about Vcc/2 is applied to the sour... | 11/20/2001 |
