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| Number | Title | Issue Date |
| 8030981 | Latency signal generating circuit and semconductor device having the same A semiconductor device includes a latency signal generating circuit for generating a latency signal corresponding CAS latency by measuring a delay amount reflected at a delay locked loop and reflecting the measured delay amount at a read command signal, and a delay ... | 10/04/2011 |
| 7952411 | Programmable digital delay A method of delaying successive first and second input signals by first and second different selectable time periods using a programmable delay line comprising a sequence of delay elements, each introducing a delay, the method comprising the steps of: providing a co... | 05/31/2011 |
| 7880524 | DLL circuit and method of controlling the same A DLL circuit includes a delay unit configured to generate a DLL clock signal by delaying a reference clock signal while adjusting a delay amount in response of a level of a control voltage. An initial operation control unit is configured to control an initial level... | 02/01/2011 |
| 7626435 | High resolution delay line architecture A delay line architecture is presented. In one embodiment, the delay line is used to introduce delay compensation into a circuit design at the top level of the circuit design. ... | 12/01/2009 |
| 7605630 | Delay circuit A delay circuit respectively delays rising and falling edges of an input signal. The delay circuit comprises first and second delay lines, a control circuit, and first and second logic circuits. The first delay line delays the first input signal the first delay time... | 10/20/2009 |
| 7576586 | Common-mode charge control in a pipelined charge-domain signal-processing circuit In a differential bucket-brigade device (BBD) pipeline it is necessary for proper circuit function to maintain the common-mode charge within an acceptable range at each pipeline stage. Embodiments of the present invention provide for reducing common-mode charge vari... | 08/18/2009 |
| 7432753 | Delay circuit and semiconductor device A delay circuit comprises: N-stage circuits having a first circuit to an N-th circuit connected in cascade, the input signal being input to the first circuit and a transmission signal delayed by a (k-1)-stage (where 2≦k≦N) circuit is input to a k-th circuit for ... | 10/07/2008 |
| 7425858 | Delay line periodically operable in a closed loop A delay line is periodically configured into a delay-locked loop for calibration purposes. That is, the delay line is operated in an open loop mode during a first time period in which a signal, such as an aperiodic signal, is the input signal into the delay line. Pe... | 09/16/2008 |
| 7425857 | Time-delay circuit A time delay logic comprises a first stage with an inverter, a capacitor connected to the input terminal of the inverter, a constant current generator and an electronic switch controlled by an input pulse. The capacitor begins to charge at a predetermined edge of th... | 09/16/2008 |
| 7417478 | Delay line circuit Methods, circuits, devices, and systems are provided, including a delay line for a delay-locked loop. One method includes providing a reference clock to a first delay unit in a delay line. The delay line includes a number of delay units coupled together. Even delay ... | 08/26/2008 |
| 7378892 | Device for setting a clock delay A device for setting a clock delay is proposed, wherein delayed output clock signals are generated with the aid of delaying means by delaying an input clock signal. The delaying means are configured to provide several differently delayed clock signals simultaneously... | 05/27/2008 |
| 7375564 | Time delay compensation circuit comprising delay cells having various unit time delays A delay-locked loop includes a phase detector, a delay line, and a filter unit. The phase detector compares the phase of the external clock signal with that of the feedback clock signal and outputs a phase difference as an error control signal. The delay line includ... | 05/20/2008 |
| 7368967 | Timing controller and controlled delay circuit for controlling timing or delay time of a signal by changing phase thereof A controlled delay circuit has a first gate chain, and a second gate chain. The first gate chain is used to measure a time difference between a changeover point of a first control signal and a changeover point of a second control signal. The second gate chain, which... | 05/06/2008 |
| 7358823 | Programmable capacitors and methods of using the same In a first aspect, a first method of adjusting capacitance of a semiconductor device is provided. The first method includes the steps of (1) providing a transistor including a dielectric material having a dielectric constant of about 3.9 to about 25, wherein the tra... | 04/15/2008 |
| 7339409 | Slew rate controlled output driver for use in semiconductor device An output driver for use in a semiconductor is capable of maintaining its slew rate constantly regardless of PVT(Process/Voltage/Temperature) variation. The output driver includes a pre-driving unit for pre-driving a data signal; a main driving unit for driving an o... | 03/04/2008 |
| 7332950 | DLL measure initialization circuit for high frequency operation A memory device, delay lock loop circuit (DLL) and DLL reset circuitry are described. The DLL includes a shift register and a measured delay for pre-loading the shift register. The reset circuitry selectively filters a clock signal propagation through the measured d... | 02/19/2008 |
| 7304520 | Delay circuit and semiconductor device including same A delay circuit comprises a plurality of delay blocks connected in series, and a driving portion adapted to logically combine signals transmitted by the plurality of delay blocks to generate a delay circuit output signal. Each of the plurality of delay blocks delays... | 12/04/2007 |
| 7301371 | Transmitter of a semiconductor device Embodiments of the present invention provide a transmitter of a semiconductor device, which can output signals corresponding to input signals having various common mode levels and amplitudes. The transmitter may include a pre-driver unit, main driver unit, and a con... | 11/27/2007 |
| 7295055 | Device for eliminating clock signal noise in a semiconductor integrated circuit A semiconductor integrated circuit includes a integration circuit which has a first integrating portion and a second integrating portion. The semiconductor integrated circuit also includes a data input portion, data processing portion and data output portion. A cloc... | 11/13/2007 |
| 7295054 | Buffer capable of controlling slew rate in drive IC The present invention relates generally to a buffer of a drive Integrated Circuit (IC) and, more particularly, to a buffer of a drive IC for driving a spatial light modulator that can meet a desired dynamic slew rate characteristic by controlling current that affect... | 11/13/2007 |
| 7285996 | Delay-locked loop A delay locked loop (DLL) circuit that includes a delay line having a plurality of delay elements. Each delay element can be adapted to receive a clock input signal and generate a clock output signal, where the phase of each clock output signal is offset from the cl... | 10/23/2007 |
| 7276946 | Measure-controlled delay circuits with reduced phase error Measure-controlled delay (MCD) circuits include a measure circuit and sample circuit for synchronizing an output clock to an input clock. In response to triggering of the measure circuit, sample circuits sample outputs of a measure delay array. Sample reset logic pr... | 10/02/2007 |
| 7248125 | Poly-phase VCO with rail to rail output voltage swing and duty cycle control across tuning range An even number phase ring oscillator having at least eight, equally spaced phases. The oscillator includes at least eight stages, defining at least four pairs of stages, with each pair including a first stage and an associated second stage. The first stages are arra... | 07/24/2007 |
| 7239185 | Driver circuit connected to pulse shaping circuitry An integrated circuit driver includes an output stage having source drain paths of a PFET and NFET connected in series with each other across DC power supply terminals. A pair of inverters simultaneously responsive to a bilevel signal drive gate electrodes of the PF... | 07/03/2007 |
| 7233185 | Vernier circuit for fine control of sample time A vernier time shifting circuit is used for fine-tuning capture of a clock signal and/or a data signal to compensate for fluctuations produced by the system or other variations within non-time invariant parts of the chip. Other variations can include process, temper... | 06/19/2007 |
| 7233325 | Structure and method for reducing source line resistance of light emitting diode A structure and a method for reducing source line resistance of a light emitting diode. A light emitting diode display has at least a light emitting diode, a power source and a power source line structure for guiding the power source to provide the required power fo... | 06/19/2007 |
| 7230498 | Delay line for a ring oscillator circuit A delay line for a ring oscillator circuit includes at least one delay stage having a multiple logic gate delay cells driven by a multiplexer. The multiplexer is symmetrically configured and includes multiple logic gates that are similar to the logic gates of the de... | 06/12/2007 |
| 7222036 | Method for providing PVT compensation Delays through components of a programmable device are determined transparently to the user through the use of mimic paths. For each delay path to be measured, at least one mimic path is created that has similar components and characteristics to the actual path to b... | 05/22/2007 |
| 7205803 | High speed fully scaleable, programmable and linear digital delay circuit The digitally programmable delay circuit to correct timing skew between data and clock is developed. The digitally programmable delay circuit may be built by cascading delay cells. The delay circuit uses delay cells comprising simple digital elements such as inverte... | 04/17/2007 |
| 7190202 | Trim unit having less jitter A trim unit includes a delay line and one or more individually selectable load elements. The delay line has a first end to receive an input clock signal, and has a second end to generate an output clock signal. Each load element includes a select transistor and a lo... | 03/13/2007 |
| 7173468 | Multiple-input, single-exit delay line architecture A delay line includes a delay chain consisting of series-connected NAND gate delay stages with a delayed output signal extracted from the final delay stage. Tap decode gates are preferably used to “inject” the input signal to be delayed into the delay chain usin... | 02/06/2007 |
| 7167035 | Delay circuitry and method therefor One use for delay adjustment circuit (32), coarse-grain delay offset circuit (34), and fine-grain delay synthesis circuit (36) may be as part of a delay replication circuit (30) used to replicate the frequency versus voltage behavior of a... | 01/23/2007 |
| 7154324 | Integrated circuit delay chains Delay chain circuitry is provided. The delay chain circuitry has a number of delay chain inverters. Each delay chain inverter is connected in series with a load resistor and has an associated capacitor between its input and ground. The electrodes of each capacitor m... | 12/26/2006 |
| 7148733 | Variable delay circuit with faster delay data update Delays induced to leading and trailing edges of an input pulse train are updated faster than before. First and second delay paths receive delay data for inducing delays to leading edges and/or trailing edges of an input pulse train. An OR circuit combines the output... | 12/12/2006 |
| 7145376 | Method and circuitry for reducing duty cycle distortion in differential delay lines A method and circuitry are provided for reducing duty cycle distortion in differential solid state delay lines. The differential solid state delay lines of the present invention include a plurality of delay line cells or stages connected in series. Because there may... | 12/05/2006 |
| 7142032 | Tunable delay circuit A delay locked loop includes a forward path for receiving an input signal to provide an output signal, a feedback path for providing a feedback signal based on the output signal, and a controller responsive to a timing relationship between the feedback signal and th... | 11/28/2006 |
| 7142031 | Delay device, semiconductor testing device, semiconductor device, and oscilloscope To enhance the accuracy of the delay time of the delay device by reducing the change in the power supply voltage for the delay device, and a delay device that delays an incoming transmission signal, comprising: a delay element that operates on a power supply voltage... | 11/28/2006 |
| 7126399 | Memory interface phase-shift circuitry to support multiple frequency ranges The present invention provides a phase shift circuit that supports multiple frequency ranges. The phase shift circuit receives a plurality of control bits and causes a phase shift in a received signal, the phase shift corresponding to a number of time steps, the num... | 10/24/2006 |
| 7110718 | Phase distortion using MOS nonlinear capacitance RF phase distortion circuits and methods for controllably phase distorting an RF signal based on amplitude of the RF signal. An MOS device is provided having a body of a first conductivity type and at least one region of a second conductivity type in the body, with ... | 09/19/2006 |
| 7106117 | Delayed clock signal generator A device which may be configured to generate delayed clock signals by a specified phase difference, which may include a clock generator circuit for generating at least one clock signal, a delayed clock signal generator for delaying the at least one clock signal, a p... | 09/12/2006 |
