Quotables
"There is no reason anyone would want a computer in their home."
Ken Olsen, chairman and founder of Digital Equipment Corporation ; 1977
PatentStorm News
Make the Most of Our Site
See this month's Top Inventors and Most Cited Patents.
Stay on top of the latest innovations by subscribing to an RSS feed.
Registered users: Manage your profile.
| Number | Title | Issue Date |
| 8008960 | Synchronous rectifier post regulator Methods and apparatus for regulating a synchronous rectifier DC-to-DC converter by adjusting one or more existing synchronous rectifiers in the converter are provided. By regulating an existing synchronous rectifier, the rectifier may function as a modulator for pos... | 08/30/2011 |
| 7667515 | Time delay apparatus and method of using same Disclosed is a time delay generator 200 apparatus and method. The apparatus includes a time delay gate 212, a mixer 216 (a Gilbert cell circuit), and a current digital to analog converter 206. The mixer 216, comprised of first and ... | 02/23/2010 |
| 7541855 | CML delay cell with linear rail-to-rail tuning range and constant output swing A current mode logic (CML) delay cell with linear rail-to-rail tuning range and constant output swing. The CML delay cell can include a tuning voltage input on a first and second transistor, contributing to a CML delay cell load, and a bias voltage input on a third ... | 06/02/2009 |
| 7446584 | Time delay apparatus and method of using same Disclosed is a time delay generator 200 apparatus and method. The apparatus includes a time delay gate 212, a mixer 216 (a Gilbert cell circuit), and a current digital to analog converter 206. The mixer 216, comprised of first and ... | 11/04/2008 |
| 7403057 | CML delay cell with linear rail-to-rail tuning range and constant output swing A current mode logic (CML) delay cell with linear rail-to-rail tuning range and constant output swing. The CML delay cell can include a tuning voltage input on a first and second transistor, contributing to a CML delay cell load, and a bias voltage input on a third ... | 07/22/2008 |
| 7385426 | Low current offset integrator with signal independent low input capacitance buffer circuit A buffer circuit (318) including a first half circuit and a second half circuit. Each half circuit includes a first MOS transistor (M4, M9) as the input device and a source follower, a second MOS transistor (M23, M22) as a transcon... | 06/10/2008 |
| 7355488 | Differential amplifier for use in ring oscillator A differential amplifier circuit for use in a ring oscillator includes first and second MOS transistors to each source of which an operating power source voltage is applied, and which individually respond to first and second input signals with mutually contrary phas... | 04/08/2008 |
| 7352826 | Analog delay circuit An analog delay circuit to impart a group delay to an analog input signal is described. The analog delay circuit may comprise a capacitor to impart at least a portion of the group delay to the analog output signal and a buffer circuit coupled between the capacitor a... | 04/01/2008 |
| 7352223 | Delay circuit having a capacitor and having reduced power supply voltage dependency A delay circuit includes: an input signal line (IN) through which an input signal is inputted; a capacitor (106) charged with and discharging electric charge; a first switch (101) connected to the input signal line and operating according to the input ... | 04/01/2008 |
| 7327184 | Low-power multi-level pulse amplitude modulation driver and semiconductor device having the driver A low-power multi-level pulse amplitude modulation (PAM) driver, and a semiconductor device having the same, in which the multi (M)-level PAM driver includes a load unit, first and second current sources, a pair of first input transistors, a pair of second input tra... | 02/05/2008 |
| 7325175 | Phase adjust using relative error A system may adjust the times at which data is sampled by separate sampling mechanisms. Here, it may be desirable to ensure that one sampler samples data at substantially the same time as the other sampler. For example, output data from a high speed sampler that sam... | 01/29/2008 |
| 7313741 | Integrated semiconductor memory An integrated semiconductor memory includes memory cells that store a first data record has at least one datum with a first or second data value and a second data record has at least one datum with the first or second data value. The integrated semiconductor memory ... | 12/25/2007 |
| 7301391 | Filtering variable offset amplifier A current summing FIR filter can be implemented with multiple differential input stages and variable tail currents. The variable tail currents can be used to appropriately weight the present and previous digital input signals. The weighted outputs of the differentia... | 11/27/2007 |
| 7287235 | Method of simplifying a circuit for equivalence checking A method of simplifying a logic circuit for enabling cycle-by-cycle equivalence checking is provided. To accomplish this, first, a logic circuit is identified to be a variable delay circuit or a fixed delay circuit. If the logic circuit is a variable delay circuit, ... | 10/23/2007 |
| 7283596 | PAM-4 data slicer having symmetrical offset A PAM-4 data slicer includes first, second, and third comparators which provide first, second, and third thresholds, respectively. Each of the comparators has an offset. The first and third comparators have an offset generating arrangement at their outputs to provid... | 10/16/2007 |
| 7282962 | Inverted-phase detector An inverted-phase detector is implemented in a system including a first clock circuit that provides a first clock signal and a delayed clock circuit that outputs an delayed clock signal. A reference circuit outputs a reference signal. A feedback circuit generates a ... | 10/16/2007 |
| 7279924 | Equalization circuit cells with higher-order response characteristics Equalization circuitry includes additional components to boost the performance of the circuitry to a higher-order response. The additional components are preferably controllably variable so that the response can be adjusted to perform a wide range of equalization ta... | 10/09/2007 |
| 7276946 | Measure-controlled delay circuits with reduced phase error Measure-controlled delay (MCD) circuits include a measure circuit and sample circuit for synchronizing an output clock to an input clock. In response to triggering of the measure circuit, sample circuits sample outputs of a measure delay array. Sample reset logic pr... | 10/02/2007 |
| 7263117 | Dual control analog delay element and related delay method A delay line including analog delay elements each having a selectively adjusted coarse and fine delay portion is described. The coarse delay portion receives an input clock signal and generates a ramp signal having a slope based on a predetermined coarse delay setti... | 08/28/2007 |
| 7257497 | Sequential frequency band acquisition apparatus for test and measurement instruments An acquisition apparatus for a test and measurement instrument includes an input to receive an input signal, a digitizer to digitize a selected signal, a bypass path to selectively couple the input to the digitizer, a frequency shift path to frequency shift the inpu... | 08/14/2007 |
| 7239494 | System and method to mitigate voltage fluctuations A system and method can mitigate voltage fluctuations. According to one embodiment, a delay system provides a delayed version of a first reference signal as a function of a supply voltage. A comparator provides a control signal for controlling a protection device ba... | 07/03/2007 |
| 7230495 | Phase-locked loop circuits with reduced lock time PLL circuits are provided in which a voltage-controlled oscillator (VCO) comprising one or more voltage-controlled delay units (VCDs) is initialized with the control voltage of a voltage-controlled delay line (VCDL) having substantially identical VCDs. In general, V... | 06/12/2007 |
| 7202726 | Voltage controlled oscillator delay cell A voltage-controlled oscillator design is disclosed that provides greater tuning range than a prior art differential amplifier design using “varactor” diodes. The design employs CMOS capacitors to replace varactor diodes. The CMOS capacitors are formed from PMOS... | 04/10/2007 |
| 7184469 | Systems and methods for injection of test jitter in data bit-streams A method for injecting test jitter in a data bit stream comprises modulating first and second voltage generators to control a rise and fall times of an output signal, respectively. A pair of input voltages are received by a differential pair. At least one current si... | 02/27/2007 |
| 7176737 | Phase-locked loop and delay-locked loop including differential delay cells having differential control inputs A differential delay cell is provided herein that not only receives a pair of differential input values, but also receives a pair of differential control values for delaying the differential input values to produce a pair of differential output values. As such, a de... | 02/13/2007 |
| 7167041 | Voltage buffer for capacitive loads A voltage buffer for capacitive loads isolates the load from the feedback loop. Using a variation of a follower arrangement, a second transistor outside of the feedback loop introduced. The current to the load is supplied through the second transistor, which is conn... | 01/23/2007 |
| 7151397 | Voltage controlled oscillator programmable delay cells A delay cell has selectable numbers of parallel load resistance transistors operable in parallel, and a similarly selectable number of bias current transistors connectable in parallel. The delay cell is preferably differential in construction and operation. A voltag... | 12/19/2006 |
| 7132857 | High speed receiver with wide input voltage range A receiver circuit (12) includes a first gate (24) that receives an input signal (VIN0, VIN1) and has an output (32, 34) for providing an output signal (VG0, VG1). A shifting circuit (20) is cou... | 11/07/2006 |
| 7132888 | Large gain range, high linearity, low noise MOS VGA An integrated receiver with channel selection and image rejection is substantially implemented on a single CMOS integrated circuit. A receiver front end provides programable attenuation and a programable gain low noise amplifier. LC filters integrated onto the subst... | 11/07/2006 |
| 7119523 | Semiconductor chip A semiconductor chip able to reduce wasteful power loss due to a margin of power supply voltage considering variation of characteristics. A voltage setting signal for setting the power supply voltage to be supplied to a target circuit is generated in a voltage contr... | 10/10/2006 |
| 7106109 | Biasing circuit and voltage control oscillator thereof A biasing circuit and a voltage control oscillator thereof are provided. The biasing circuit comprises a compensation circuit, a delay circuit and a comparison circuit. In the biasing circuit, the compensation circuit compensates a first differential voltage that is... | 09/12/2006 |
| 7082172 | Digital signal gating apparatus and method in a pulse receiver system A digital signal gating method and apparatus of a preprocessor in a detection system wherein the detection system includes a central processing unit, a main memory and a receiver, whereby the apparatus and method bifurcate received digital signals, delays them along... | 07/25/2006 |
| 7057450 | Noise filter for an integrated circuit A noise filter for an integrated circuit is proposed. The noise filter comprises a CMOS inverter and two capacitors. The input of the CMOS inverter is coupled with an input pad of the integrated circuit and the output of the CMOS inverter is coupled with an input bu... | 06/06/2006 |
| 7019590 | Self-stabilizing differential load circuit with well controlled impedance A circuit for providing a self-stabilizing, differential load circuit with well controlled impedance to an amplifier is described. According to one embodiment, two pairs of transistors in a cross-coupled configuration and a degeneration resistor for each transistor ... | 03/28/2006 |
| 7010563 | Multiplier with output current scaling A multiplier includes an input stage to receive input signals to provide currents at a plurality of source nodes. An output stage includes a plurality of transistor groups, each of the transistor groups includes a plurality of transistor pairs. The values of current... | 03/07/2006 |
| 6972634 | Interconnected multi-stage oscillator The invention provides an oscillator apparatus having a plurality of stages, with each stage of the plurality of stages having an output node, and with a plurality of input transistors within each stage. The various output nodes are coupled to the transistor inputs ... | 12/06/2005 |
| 6958640 | Interpolation delay cell for 2ps resolution jitter injector in optical link transceiver An apparatus and method for generating signals with improved timing resolution includes a delay cell configured to receive dual coupled differential input signals. The delay cell performs an interpolation function which smooths state transitions or other discontinui... | 10/25/2005 |
| 6949984 | Voltage controlled oscillator having control current compensation A voltage controlled oscillator (600) includes a voltage to current portion (400) that is inversely proportional to the semiconductor processing in order to compensate for variations both in the low-frequency and high-frequency portions of the VCO gain... | 09/27/2005 |
| 6946902 | Filtering variable offset amplifier A current summing FIR filter can be implemented with multiple differential input stages and variable tail currents. The variable tail currents can be used to appropriately weight the present and previous digital input signals. The weighted outputs of the differentia... | 09/20/2005 |
| 6943603 | Pulse generating circuit and semiconductor device provided with same A pulse generating circuit generates a pulse with a desired pulse width even when a process parameter for manufacturing fluctuates or a source voltage varies. The pulse generating circuit includes a first voltage outputting section having a first delay circuit and o... | 09/13/2005 |
