Celebrity Inventors
Glam girl Heddy Lamar may have used her good looks to good effect on the silver screen, but she put her smarts to better use as an inventor. During World War II, she co-patented a frequency-switching system for torpedo guidance that was considered years ahead of its time.
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| Number | Title | Issue Date |
| 7982516 | RC-based delay element and method for reducing frequency induced delay variation A programmable delay element with a variable delay generator employs feed forward and feedback control signals to corresponding feed forward and feedback control elements integrated within the variable delay generator. The variable delay generator is responsive to a... | 07/19/2011 |
| 7545195 | Variable delay element A variable delay element includes first and second input stages, each input stage comprising a charge pumping circuit and a discharging circuit, each charge pumping circuit and each discharging circuit associated with the first and second input stages configured to ... | 06/09/2009 |
| 7436235 | Digital clock modulator A digital clock modulator provides a smoothly modulated clock period to reduce emitted electro-magnetic radiation (EMR). The digital clock modulator includes a plurality of delay elements connected in series and receiving as an input an unmodulated clock signal. A m... | 10/14/2008 |
| 7425858 | Delay line periodically operable in a closed loop A delay line is periodically configured into a delay-locked loop for calibration purposes. That is, the delay line is operated in an open loop mode during a first time period in which a signal, such as an aperiodic signal, is the input signal into the delay line. Pe... | 09/16/2008 |
| 7414450 | System and method for adaptive power supply to reduce power consumption A system and method for adaptively providing a power supply voltage. The system includes an oscillator configured to receive an output voltage and generate a firs signal. The first signal is associated with a first frequency and a first period. Additionally, the sys... | 08/19/2008 |
| 7403056 | Delay apparatus and method thereof The present invention provides a delay apparatus for delaying an input signal by a predetermined delay amount, including: a plurality of delay units for respectively delaying the input signal by the predetermined delay amount, each delay unit having a plurality of d... | 07/22/2008 |
| 7394302 | Semiconductor circuit, operating method for the same, and delay time control system circuit A semiconductor circuit allows a timing adjustment after detailed routing without rearrangement and rerouting, an adjustment of delay variance due to process variation, and a delay adjustment even after chip formation using a primitive cell with a built-in means for... | 07/01/2008 |
| 7391247 | Timing vernier using a delay locked loop A method for synchronizing a plurality of programmable timing verniers with a reference pulse signal, each of the verniers being programmable to one of a plurality of timing steps within a delay range determined by a control signal applied to a bias input. A first a... | 06/24/2008 |
| 7375569 | Last stage synchronizer system A pulse jitter reduction circuit employs a low jitter system clock coupled to synchronize a pulse generating device and an ultra low jitter flip-flop to generate substantially jitter-free trigger signals employed to generate high voltage pulses for a flight tube of ... | 05/20/2008 |
| 7375564 | Time delay compensation circuit comprising delay cells having various unit time delays A delay-locked loop includes a phase detector, a delay line, and a filter unit. The phase detector compares the phase of the external clock signal with that of the feedback clock signal and outputs a phase difference as an error control signal. The delay line includ... | 05/20/2008 |
| 7368967 | Timing controller and controlled delay circuit for controlling timing or delay time of a signal by changing phase thereof A controlled delay circuit has a first gate chain, and a second gate chain. The first gate chain is used to measure a time difference between a changeover point of a first control signal and a changeover point of a second control signal. The second gate chain, which... | 05/06/2008 |
| 7366267 | Clock data recovery with double edge clocking based phase detector and serializer/deserializer A programmable logic device (“PLD”) is augmented with programmable clock data recover (“CDR”) circuitry to allow the PLD to communicate via any of a large number of CDR signaling protocols. The CDR circuitry may be integrated with the PLD, or it may be wholl... | 04/29/2008 |
| 7366966 | System and method for varying test signal durations and assert times for testing memory devices A testing system includes a phase interpolator receiving a clock signal. An output of the phase interpolator is coupled to both a first signal distribution tree that includes a first delay line in each of its branches and a second signal distribution tree that inclu... | 04/29/2008 |
| 7366940 | Multiprotocol computer bus interface adapter and method A predictive time base generator having predictive synchronizer and replica delay element coupled with the synchronizer feedback delay loop. The predictive time base generator receives a clock signal delayed by a predetermined clock delay and produces a predictive t... | 04/29/2008 |
| 7363401 | Method and apparatus for controlling bus transactions depending on bus clock frequency A method and apparatus is presented that can provide first and second windows for driving data onto a bus in dependence on bus clock frequency. In one example, the speed of the bus clock is determined by a component such as a processor. If the bus clock frequency is... | 04/22/2008 |
| 7362155 | Method and apparatus for generating delays One embodiment pertains generally to a method of delaying based on a single clock signal. The method includes providing a first clock signal and generating a second clock signal based on the first clock signal and a third clock signal that is the inverse of the seco... | 04/22/2008 |
| 7355435 | On-chip detection of power supply vulnerabilities On-chip sensor to detect power supply vulnerabilities. The on-chip sensor employs a sensitive delay chain and an insensitive delay chain to detect power supply undershoots and overshoots without requiring external off-chip components. Undershoots and overshoots outs... | 04/08/2008 |
| 7355458 | Output driver circuit and a method of transmitting an electrical signal via an output driver circuit In an output driver circuit, the signal propagation time of an electrical signal which is to be transmitted between two selected driver stages is ascertained. If the ascertained signal propagation time is at least equal to half the period duration of the signal whic... | 04/08/2008 |
| 7352826 | Analog delay circuit An analog delay circuit to impart a group delay to an analog input signal is described. The analog delay circuit may comprise a capacitor to impart at least a portion of the group delay to the analog output signal and a buffer circuit coupled between the capacitor a... | 04/01/2008 |
| 7352223 | Delay circuit having a capacitor and having reduced power supply voltage dependency A delay circuit includes: an input signal line (IN) through which an input signal is inputted; a capacitor (106) charged with and discharging electric charge; a first switch (101) connected to the input signal line and operating according to the input ... | 04/01/2008 |
| 7348821 | Programmable high-resolution timing jitter injectors high-resolution timing jitter injectors A device includes a first circuit having rows and columns of delay cells to generate delayed signals based on an input signal. The delayed signals are selectable and have a different delay from one another with respect to the input signal. The device is programmable... | 03/25/2008 |
| 7339407 | DLL circuit for providing an adjustable phase relationship with respect to a periodic input signal The invention relates to a DLL circuit for providing an adjustable time delay of a periodic input signal, said circuit having controllable delay elements which are connected in series and form a delay chain, having a phase detector in order to generate a control sig... | 03/04/2008 |
| 7332780 | Inverter, semiconductor logic circuit, static random access memory and data latch circuit A dual structure is introduced to the transistor in a flip-flop or a data input step controlled by a clock of a semiconductor logic circuit. The dual structure is formed by connecting a transistor with a MOS transistor having a channel of the same conductivity type ... | 02/19/2008 |
| 7333527 | EMI reduction using tunable delay lines The clock signal is the dominant source of electromagnetic interference (EMI) for many digital electronic devices. EMI generated by these electronic devices must be suppressed to avoid interference with other electronic devices and to satisfy FCC regulations. The pr... | 02/19/2008 |
| 7332950 | DLL measure initialization circuit for high frequency operation A memory device, delay lock loop circuit (DLL) and DLL reset circuitry are described. The DLL includes a shift register and a measured delay for pre-loading the shift register. The reset circuitry selectively filters a clock signal propagation through the measured d... | 02/19/2008 |
| 7333570 | Clock data recovery circuitry associated with programmable logic device circuitry A programmable logic device (“PLD”) is augmented with programmable clock data recover (“CDR”) circuitry to allow the PLD to communicate via any of a large number of CDR signaling protocols. The CDR circuitry may be integrated with the PLD, or it may be wholl... | 02/19/2008 |
| 7324048 | Wavelength division multiplexing methods and apparatus for constructing photonic beamforming networks Methods and apparatus for constructing phased array antenna beamforming networks are provided, that allow to scan multiple beams and select appropriate sets of delay lines simultaneously. The beamforming networks disclosed herein generate less losses than convention... | 01/29/2008 |
| 7319345 | Wide-range multi-phase clock generator A wide-range multi-phase clock generator having a first clock generating circuit, a frequency divider circuit, and a plurality of multiplexers. The first clock generating circuit generates a plurality of first clock signals, each having a first frequency and a respe... | 01/15/2008 |
| 7319706 | Symmetrical clock distribution in multi-stage high speed data conversion circuits The present invention provides a high speed bit stream data conversion circuit that includes input ports to receive first bit streams at a first bit rate. Data conversion circuits receive the first bit streams and produce second bit stream(s), wherein the number and... | 01/15/2008 |
| 7315270 | Differential delay-line analog-to-digital converter Differential delay-line analog-to-digital (A/D) converters for use in current and power sensing applications are provided. These A/D converters are well suited for a wide range of electronic applications, including over-load protection, current mode control, current... | 01/01/2008 |
| 7313210 | System and method for establishing a known timing relationship between two clock signals A system and method for establishing a known timing relationship between two clock signals, wherein a first clock signal is operable to clock data transfer operations from a transmitter domain to a receiver domain and a second clock signal is operable to be transpor... | 12/25/2007 |
| 7310008 | Configurable delay chain with stacked inverter delay elements A stacked inverter delay chain. The stacked inverter delay chain includes a plurality of stacked inverter delay elements. A switch circuit is included and is coupled to the stacked inverter delay elements and configured to select at least one of the plurality of sta... | 12/18/2007 |
| 7304516 | Method and apparatus for digital phase generation for high frequency clock applications An apparatus and method for generating phase-related clocks are disclosed. A clock input is delayed by an alignment magnitude to generate a first phase signal. The first phase signal is delayed by the phase alignment magnitude to generate a first phase delay signal.... | 12/04/2007 |
| 7304520 | Delay circuit and semiconductor device including same A delay circuit comprises a plurality of delay blocks connected in series, and a driving portion adapted to logically combine signals transmitted by the plurality of delay blocks to generate a delay circuit output signal. Each of the plurality of delay blocks delays... | 12/04/2007 |
| 7292086 | Delay circuit and semiconductor device A delay circuit comprises: N-stage circuits having a first circit to a N-th circuit connected in cascade, the input signal being input to the first circuit and a transmission signal delayed by a (k-1)-stage (where 2≦k≦N) circuit is input to a k-th circuit for se... | 11/06/2007 |
| 7288973 | Method and apparatus for fail-safe resynchronization with minimum latency A method and circuit for achieving minimum latency data transfer between two mesochronous (same frequency, different phase) clock domains is disclosed. This circuit supports arbitrary phase relationships between two clock domains and is tolerant of temperature and v... | 10/30/2007 |
| 7286000 | Semiconductor device A semiconductor device can accurately control the timings of various signals used in the semiconductor device using a simple configuration. The semiconductor device includes first fuse units which output first fuse signals, respectively, a first decoder which receiv... | 10/23/2007 |
| 7285996 | Delay-locked loop A delay locked loop (DLL) circuit that includes a delay line having a plurality of delay elements. Each delay element can be adapted to receive a clock input signal and generate a clock output signal, where the phase of each clock output signal is offset from the cl... | 10/23/2007 |
| 7284216 | System and method for verifying signal propagation delays of circuit traces of a PCB layout A system for verifying signal propagation delays of circuit traces of a printed circuit board (PCB) layout includes a computer (1). The computer includes: a setting module (10) for setting a minimum propagation delay and a maximum propagation delay for... | 10/16/2007 |
| 7283005 | Clock-pulse generator circuit The circuit comprises a first ring oscillator comprising an odd number of inverting elements, a delay element and an output terminal; the delay element responds to a pulse at its input with a predetermined time delay with respect to a predetermined edge of the input... | 10/16/2007 |
