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| Number | Title | Issue Date |
| 8179181 | Power-mode-aware clock tree and synthesis method thereof A power-mode-aware (PMA) clock tree and a synthesis method thereof are provided. The clock tree includes a sub clock tree and a PMA buffer. The sub clock tree transmits a delayed clock signal to a function module, wherein a power mode of the function module is deter... | 05/15/2012 |
| 8120409 | Programmable delay circuit with integer and fractional time resolution A programmable delay circuit capable of providing a delay with integer and fractional time resolution is described. In one exemplary design, an apparatus includes first and second delay circuits. The first delay circuit provides a first delay of an integer number of... | 02/21/2012 |
| 7944264 | Variable delay circuit, variable delay circuit controlling method, and input/output circuit A variable delay circuit includes: a first delay section that changes a first drive capability or a first capacity load, receives the reference signals, and generates a first delayed signal by giving a first delay to the reference signal; a second delay section that... | 05/17/2011 |
| 7932766 | Digitally controlled oscillator with the wide operation range There is provided a digitally controlled oscillator, which is capable of widening its operation range with maintaining its resolution and the maximum frequency at which it operates. The digitally controlled oscillator includes a phase compensation block, a coarse bl... | 04/26/2011 |
| 7920005 | Large time constant steering circuit and instrumentation amplifier implementing same The present invention relates to a large time constant steering circuit for slowly changing a voltage on a node between at least two discrete voltage levels. The present invention further relates to a slow steering current DAC comprising said large time constant ste... | 04/05/2011 |
| 7898312 | Variable delay apparatus It is an object of the invention to provide a variable delay apparatus in which, even immediately after the delay amount of the variable delay apparatus is changed, a signal of a timing that is different from a set delay amount is not output. The variable delay appa... | 03/01/2011 |
| 7834673 | Variable delay circuit and delay amount control method A variable delay circuit comprising a first delay element configured to delay an input signal, a second delay element coupled to the first delay element in parallel and also configured to delay the input signal, a control current supply section configured to supply ... | 11/16/2010 |
| 7834674 | Delay circuit and delay locked loop circuit including the same A delay circuit includes a delay line unit including a plurality of delay units configured to generate a plurality of delay input clocks by delaying an input clock by a unit delay amount in response to at least one delay control signal; and a signal selection unit c... | 11/16/2010 |
| 7830192 | Delay circuit and related method thereof A delay circuit comprising a delay measurement unit, a delay mapping unit and a map delay module. The delay measurement unit generates a mapping table according to a reference signal and a reference clock signal. The delay mapping unit generates a mapped delay selec... | 11/09/2010 |
| 7825713 | Absolute time delay generating device An absolute time delay generating device includes a PVT (process-voltage-temperature) detection device and a delay-timing generator. The PVT detection device includes at least a delay module and a signal phase/frequency control module. The delay module includes a co... | 11/02/2010 |
| 7786784 | Variable delay circuit, variable delay device, and VCO circuit Herein disclosed is a variable delay circuit, including a first delay portion that delays an input signal; an output portion; and a variable impedance portion provided coupled between the first delay portion and an the output portion. ... | 08/31/2010 |
| 7782109 | Delay circuit and related method A delay circuit includes a first delay module, a delay measurement unit and a fault judge unit. The first delay module has a first delay circuit with at least one delay stage. The delay measurement unit is used for measuring a first delay amount and a second delay a... | 08/24/2010 |
| 7750712 | Timing control circuit, timing generation system, timing control method and semiconductor memory device A timing control circuit DLY1 receives clock signal CKa with period T1 and activation signal ACT and outputs fine timing signal FT with delay of m*T1+tda measured from the clock signal where m denotes a non-negative integer and tda denotes delay... | 07/06/2010 |
| 7750711 | Phase select circuit with reduced hysteresis effect A phase signal select circuit includes a supporting path coupled to a tri-state inverter circuit. The supporting path reduces effects of hysteresis on signal transfer. An apparatus includes at least one input node responsive to a respective one of at least one input... | 07/06/2010 |
| 7750710 | Delay circuit A delay circuit has a second delay element 8 supplied with a delay time control signal Vcntl from a frequency variable oscillator 2 including a first delay element 8 of which delay time as a concomitant of signal propagation is controlled by a d... | 07/06/2010 |
| 7728643 | Delay circuit and semiconductor memory device including the same A delay circuit that includes a logic gate through which an input signal passes, a capacitor configured to be charged and discharged at an output terminal of the logic gate and delaying the input signal, and a mirroring unit configured to constantly maintain current... | 06/01/2010 |
| 7714629 | Delay circuit and delay time adjustment method A delay circuit includes an interface for giving a command of setting a delay time and a delay device that can be set to any desired delay time, and the delay time of the delay device is set according to a command from the interface. ... | 05/11/2010 |
| 7705651 | Delay circuit of semiconductor memory apparatus A delay circuit of a semiconductor memory apparatus can include a clock period sensing unit for generating a sensing signal in response to a clock frequency, and a selective delay unit for delaying an input signal for a delay time and then output the input signal as... | 04/27/2010 |
| 7696803 | Signal generating circuit A signal generating circuit includes an input stage delay circuit which can switch a state of outputting a reference clock and a state of outputting a signal delaying the reference clock by a first time which is shorter than one cycle of the reference clock, a contr... | 04/13/2010 |
| 7667514 | Delay circuit and electronic device including delay circuit A delay circuit includes: a current control circuit which has n (n is 1 or larger natural number) control pins and a first output line, and is capable of controlling current outputted from the first output line in response to n control signals inputted to the corres... | 02/23/2010 |
| 7656212 | Configurable delay chain with switching control for tail delay elements A configurable delay chain with switching control. The configurable delay chain includes a plurality of delay elements. A switch circuit is included and is coupled to the delay elements and configured to select at least one of the plurality of delay elements to crea... | 02/02/2010 |
| 7629825 | Efficient delay elements Circuits, methods, and apparatus for delaying signals in a power and area efficient manner are provided. A gating element within a stage of a programmable delay element suppresses an operation of other stages of the delay element. A programmable delay has components... | 12/08/2009 |
| 7619457 | Programmable delay circuit A delay circuit is described having a variable capacitor and a triggering circuit. The variable capacitor and the triggering circuit may both comprise transistors. With both the variable capacitor and the triggering circuit dependent on the threshold voltage, the de... | 11/17/2009 |
| 7583124 | Delaying stage selecting circuit and method thereof A delaying stage selecting circuit for selecting a specific delaying stage from a plurality of delaying stages, where the delaying stages are for outputting delayed clock signals, includes: a first register for sampling the delayed clock signals according to a clock... | 09/01/2009 |
| 7576585 | Delay circuit A delay circuit, including: a plurality of first delay units coupled in series and each configured to generate a delay time that is approximately double a unit delay time; a second delay unit configured to generate the unit delay time and coupled to a last stage of ... | 08/18/2009 |
| 7570097 | Electronic circuit with low noise delay circuit An electronic circuit comprises a delay circuit that with a chain of saw tooth delay stages (10a-d), coupled in a loop to form an oscillator for example. Each stage comprises an integrating circuit (104) and a current modulator (106 | 08/04/2009 |
| 7564285 | Controllable delay line and regulation compensation circuit thereof A controllable delay line includes an anti-jitter unit, a dependent current source, a first current mirror, a second current mirror, a regulation capacitor, a compensation capacitor and an output buffer unit. The anti-jitter unit receives a first bias voltage and pr... | 07/21/2009 |
| 7548105 | Method and apparatus for source synchronous testing A method and apparatus for source synchronous testing have been disclosed. In one case a data signal is delayed and a selectively activated delay is applied to a clock. This allows the clock to be positioned before the data and also after the data. ... | 06/16/2009 |
| 7545194 | Programmable delay for clock phase error correction A method, circuit, and system are disclosed. In one embodiment, the method comprises receiving a differential clock signal from two clock signal lines into a first differential pair of transistors of a first size, receiving the differential clock signal from the two... | 06/09/2009 |
| 7525364 | Delay control circuit A first variable delay circuit delays an input signal, introduces a first delay into a first edge of the input signal, and generates a first delay signal. A second variable delay circuit delays the input signal, introduces a second delay into a second edge, and gene... | 04/28/2009 |
| 7521977 | Voltage-controlled oscillator generating output signal finely tunable in wide frequency range and variable delay circuits included therein A voltage-controlled oscillator includes a plurality of variable delay circuits, wherein a first differential output signal of an adjacent previous stage is provided as a first differential input signal and a second differential output signal of a second previous st... | 04/21/2009 |
| 7511547 | Delay circuit, and testing apparatus A delay circuit for delaying an input signal according to a desired delay time setting and outputting the same is provided. The delay circuit includes: a delay element for delaying the input signal for a delay time based on a given supply current and outputting the ... | 03/31/2009 |
| 7504872 | Generic flexible timer design One embodiment of the present invention sets forth a set of three building block circuits for designing a flexible timing generator for an integrated circuit. The first and second building blocks include delay elements that may be customized and fine-tuned prior to ... | 03/17/2009 |
| 7495495 | Digital I/O timing control When certain digital circuit devices receive data bus signals, I/O interfaces need to sample the data signals during a time when these signals are both valid and stable. Typically, the data signals are sampled at a time corresponding to a point halfway between risin... | 02/24/2009 |
| 7492204 | Generic flexible timer design One embodiment of the present invention sets forth a set of three building block circuits for designing a flexible timing generator for an integrated circuit. The first and second building blocks include delay elements that may be customized and fine-tuned prior to ... | 02/17/2009 |
| 7456671 | Hierarchical scalable high resolution digital programmable delay circuit A hierarchical and modular clock programmable delay circuit structure is described that can achieve almost unlimited fine resolution and unlimited delay range. The same circuit may also be applied to critical circuits that require fine adjustment in timing applicati... | 11/25/2008 |
| 7411434 | Digitally programmable delay circuit with process point tracking A digitally programmable delay circuit comprising a plurality of transistors connected in parallel with each other and to a line carrying a signal having an edge to be delayed. One or more of the transistors are selected by a delay control signal to impose a delay a... | 08/12/2008 |
| 7403056 | Delay apparatus and method thereof The present invention provides a delay apparatus for delaying an input signal by a predetermined delay amount, including: a plurality of delay units for respectively delaying the input signal by the predetermined delay amount, each delay unit having a plurality of d... | 07/22/2008 |
| 7394301 | System and method for dynamically varying a clock signal According to at least one embodiment, a system comprises means for performing an operation utilizing a clock signal. The system further comprises means for supplying a variable operating voltage to the performing means, and means for dynamically varying the frequenc... | 07/01/2008 |
| 7394302 | Semiconductor circuit, operating method for the same, and delay time control system circuit A semiconductor circuit allows a timing adjustment after detailed routing without rearrangement and rerouting, an adjustment of delay variance due to process variation, and a delay adjustment even after chip formation using a primitive cell with a built-in means for... | 07/01/2008 |
