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| Number | Title | Issue Date |
| 8125261 | Multi-power source semiconductor device In a multi-supply-voltage semiconductor device including multiple blocks each of which has independent clock circuit, and operating with variable power supply, variable delay circuit which changes the amount of delay in accordance with the voltage value of the varia... | 02/28/2012 |
| 7999592 | Delay circuit of semiconductor device A delay circuit of a semiconductor device increases its delay time as an external voltage increases. The delay circuit can also ensure a desired delay time according to an external voltage, without additional delay circuits. The delay circuit of the semiconductor de... | 08/16/2011 |
| 7977994 | Digital pulse-width-modulator with discretely adjustable delay line A hybrid digital pulse width modulator (DPWM) with digital delay-locked loops (DLLs) is provided. In this implementation, the digital pulse-width-modulator is synthesizable and includes a digital delay-locked loop around a delay-line to achieve constant frequency cl... | 07/12/2011 |
| 7884660 | Variable-length digitally-controlled delay chain with interpolation-based tuning A programmable delay element, variable-length delay chain, and ring oscillator are disclosed. The programmable delay element performs phase interpolation of input signals in response to a control signal and can be used in combination with other delay elements to cre... | 02/08/2011 |
| 7777545 | Semiconductor device and timing adjusting method for semiconductor device In a semiconductor device, a delaying circuit is configured to delay an input signal based on an internal setting data to output as a timing signal. A delay determining section is configured to determine a delay state of each of a plurality of delay signals obtained... | 08/17/2010 |
| 7755407 | Variable delay circuit, testing apparatus, and electronic device Provided is a variable delay circuit outputting an output signal delayed with respect to an input signal by a designated delay time, including: a delay controller outputting a control voltage according to the delay time; a MOS transistor receiving the control voltag... | 07/13/2010 |
| 7733149 | Variable-length digitally-controlled delay chain with interpolation-based tuning A programmable delay element, variable-length delay chain, and ring oscillator are disclosed. The programmable delay element performs phase interpolation of input signals in response to a control signal and can be used in combination with other delay elements to cre... | 06/08/2010 |
| 7495494 | Parallel trimming method and apparatus for a voltage controlled delay loop A parallel trimming method and apparatus are provided for a voltage controlled delay loop. A plurality of delay units in a voltage controlled delay loop are trimmed. Each delay unit comprises a delay element and a latch buffer. A reference signal is applied to each ... | 02/24/2009 |
| 7411434 | Digitally programmable delay circuit with process point tracking A digitally programmable delay circuit comprising a plurality of transistors connected in parallel with each other and to a line carrying a signal having an edge to be delayed. One or more of the transistors are selected by a delay control signal to impose a delay a... | 08/12/2008 |
| 7403056 | Delay apparatus and method thereof The present invention provides a delay apparatus for delaying an input signal by a predetermined delay amount, including: a plurality of delay units for respectively delaying the input signal by the predetermined delay amount, each delay unit having a plurality of d... | 07/22/2008 |
| 7394301 | System and method for dynamically varying a clock signal According to at least one embodiment, a system comprises means for performing an operation utilizing a clock signal. The system further comprises means for supplying a variable operating voltage to the performing means, and means for dynamically varying the frequenc... | 07/01/2008 |
| 7373575 | Method and apparatus for generating expect data from a captured bit pattern, and memory device using same Expect data signals are generated for a series of applied data signals having a known sequence to determine if groups of the data signals were properly captured. A first group of the applied data signals is captured, and a group of expect data signals are generated ... | 05/13/2008 |
| 7372289 | Semiconductor integrated circuit device and power supply voltage monitor system employing it A semiconductor integrated circuit device, i.e. a reset IC(1), includes: a detection circuit (4) for detecting whether an input voltage (Vin) has risen or dropped by comparing the input voltage (Vin) with a reference voltage; a delay circuit (8)... | 05/13/2008 |
| 7373571 | Achieving desired synchronization at sequential elements while testing integrated circuits using sequential scan techniques A programmable delay circuit is provided in either data input path or a clock input path of a sequential element contained in a scan chain of an integrated circuit. The scan chain is used to test the integrated circuit using a sequential scan technique (e.g., Automa... | 05/13/2008 |
| 7362121 | Self-heating mechanism for duplicating microbump failure conditions in FPGAs and for logging failures A system replicates the rapid temperature increases that are believed to cause microbump failures in certain applications of programmable logic devices (PLDs). The system configures a PLD under test with a circuit that switches a large amount of current and generate... | 04/22/2008 |
| 7355465 | Delay circuit with accurate time to frequency conversion A delay circuit comprises a signal generator and a delay component. The signal generator comprises a terminal for receiving a trigger signal and an output for outputting a signal when receiving a trigger signal with a pre-determined characteristic. The delay mean co... | 04/08/2008 |
| 7352222 | Clock generator with programmable non-overlapping-clock-edge capability A system and method for generating and optimizing clock signals with non-overlapping edges on a chip using a unique programmable on-chip clock generator. Overlapping of the edges of the clocking signals is avoided by adjusting an amount of delay introduced in the on... | 04/01/2008 |
| 7352755 | Network interface card (NIC) with phase lock rise time control generating circuit A Network Interface Card (NIC) for attaching data terminal equipment to a communications network. The NIC includes a Phase Lock Loop (PLL) with a master delay structure that is operatively coupled to at least one delay line structure. The PLL generates control pulse... | 04/01/2008 |
| 7336548 | Clock generating circuit with multiple modes of operation A clock generating circuit includes a phase comparison circuit that generates a delay control signal corresponding to the relative phases of an output clock signal and a reference clock signal. A voltage controlled delay circuit generates the delayed clock signal by... | 02/26/2008 |
| 7333527 | EMI reduction using tunable delay lines The clock signal is the dominant source of electromagnetic interference (EMI) for many digital electronic devices. EMI generated by these electronic devices must be suppressed to avoid interference with other electronic devices and to satisfy FCC regulations. The pr... | 02/19/2008 |
| 7327174 | Fast locking mechanism for delay lock loops and phase lock loops A fast lock mechanism for delay lock loops and phase lock loops. A first circuit is coupled to receive an input clock signal and to generate an output clock signal responsive to the input clock signal. The first circuit includes a charge pump and delay cells. The ch... | 02/05/2008 |
| 7323918 | Mutual-interpolating delay-locked loop for high-frequency multiphase clock generation A delay-locked loop (DLL) circuit with mutual-interpolating architecture that provides multiple-phase clock generation is presented. Each delay-cell in the DLL circuit delay chain is effectively an interpolator that combines two input clock signals: one input clock ... | 01/29/2008 |
| 7313051 | Output control signal generating circuit An output control signal generating circuit includes latch circuits that are connected in cascade, and a timing signal generating circuit that generates a timing signal to be supplied to the latch circuits, based on a second clock of which phase is advanced from the... | 12/25/2007 |
| 7313491 | Method and apparatus for high-precision measurement of frequency A method and apparatus for measuring the frequency of a cyclically-repeating electrical signal by: passing the electrical signal through a network of sequentially-activated gates, in which the first gate detects the leading edge of each cycle of the electrical signa... | 12/25/2007 |
| 7312629 | Programmable impedance control circuit calibrated at Voh, Vol level A method and apparatus are provided for a programmable impedance control circuit. In one example of the apparatus, a programmable impedance control circuit of an output driver of an input/output interface is provided. The programmable impedance control circuit inclu... | 12/25/2007 |
| 7308372 | Phase jitter measurement circuit A method, an apparatus, and a system for phase jitter measurement circuits are described herein. ... | 12/11/2007 |
| 7304521 | Delay circuit for synchronizing arrival of a clock signal at different circuit board points A clock signal generation system and method to distribute at least one clock signal to a plurality of points on a circuit board using a plurality of digitally programmable delay circuits each of which delays the clock signal by a desired amount so as to synchronize ... | 12/04/2007 |
| 7298192 | Digital DLL device, digital DLL control method, and digital DLL control program A digital DLL device is provided which can reduce an error with respect to a target delay amount. The device provides a delay to an input clock signal so as to equally divide a clock cycle T thereof into N parts, and includes first variable delay sections and second... | 11/20/2007 |
| 7292486 | Methods and circuits for latency control in accessing memory devices Methods of providing a delay for access to a memory device can include adjusting a delay for access to data during memory operations based on at least one parameter associated with a reduction in voltage levels provided to the memory. Related circuits are also discl... | 11/06/2007 |
| 7283005 | Clock-pulse generator circuit The circuit comprises a first ring oscillator comprising an odd number of inverting elements, a delay element and an output terminal; the delay element responds to a pulse at its input with a predetermined time delay with respect to a predetermined edge of the input... | 10/16/2007 |
| 7279938 | Delay chain integrated circuits having binary-weighted delay chain units with built-in phase comparators therein Delay-locked loop integrated circuits include a delay chain having a plurality of delay chain units. The delay chain may be a binary-weighted delay chain and the delay chain units may be arranged in ascending or descending order (e.g., x1, x2, x4, x8, . . . ) accord... | 10/09/2007 |
| 7279944 | Clock signal generator with self-calibrating mode A clock signal generator and method thereof are provided for a system to generate an output signal. The apparatus comprises: a delay circuit for generating a delayed clock with a first time, a delay module for generating delayed signal(s), and a decision circuit for... | 10/09/2007 |
| 7276950 | Prevention of the propagation of jitters in a clock delay circuit The clock delay circuit according to the present invention includes a delay circuit section, a selection circuit section, and jitter suppression elements. The delay circuit section provides a plurality of delay clock signals that are obtained by delaying a clock sig... | 10/02/2007 |
| 7274223 | Semiconductor device As devices are often different in the characteristics from one another, semiconductor chips based on the devices have discrepancies in the performance. A semiconductor device having a semiconductor switching element and a drive controlling means (1) for gener... | 09/25/2007 |
| 7271637 | Circuit and method of controlling a delay of a semiconductor device A delay control circuit capable of controlling a delay time is disclosed. The delay control circuit includes a delay detecting circuit, a first pulse generator, a counter control circuit and a counter. The delay detecting circuit delays an input signal by a first ti... | 09/18/2007 |
| 7269754 | Method and apparatus for flexible and programmable clock crossing control with dynamic compensation A system and method for crossing clocks from a source clock to a destination clock is disclosed. In one embodiment, a source clock phase enable signal is used to enable a set of latch components to selectively input a source clock pulse. The outputs of the latch com... | 09/11/2007 |
| 7263117 | Dual control analog delay element and related delay method A delay line including analog delay elements each having a selectively adjusted coarse and fine delay portion is described. The coarse delay portion receives an input clock signal and generates a ramp signal having a slope based on a predetermined coarse delay setti... | 08/28/2007 |
| 7256636 | Voltage controlled delay line (VCDL) having embedded multiplexer and interpolation functions A voltage controlled delay line (VCDL). The VCDL includes one or more cells. Each of the one or more cells includes two or more inputs and an output. Each of the one or more cells is configured to provide a delay as well as an interpolation function and a multiplexe... | 08/14/2007 |
| 7249290 | Deskew circuit and disk array control device using the deskew circuit, and deskew method A deskew circuit includes, for clock and every bit of data, a variable delay circuit between a receiver that receives data and a flip-flop that first latches the data, in which a detecting pattern to detect a stable region for receiving data is repeatedly sent befor... | 07/24/2007 |
| 7236034 | Self correcting scheme to match pull up and pull down devices The self correcting scheme to match pull up and pull down devices includes: a first comparator for comparing a common mode signal to a high reference limit; a second comparator for comparing the common mode signal to a low reference limit; a first flip flop having a... | 06/26/2007 |
