Bizarre Patents
A coffin, for allowing inclination for display of a deceased person in a natural position.
PatentStorm News
Make the Most of Our Site
See this month's Top Inventors and Most Cited Patents.
Stay on top of the latest innovations by subscribing to an RSS feed.
Registered users: Manage your profile.
| Number | Title | Issue Date |
| 8179180 | Device and method for detecting an approach or contact A device for detecting an approach or a touch related to at least one sensor element, in particular in an electrical appliance, the device comprising an input side and an output side, between which a first signal path with a first input and a first output and a seco... | 05/15/2012 |
| 7999591 | Deskew system for eliminating skew between data signals and clock and circuits for the deskew system A deskew system includes a first voltage control delay receiving a data signal and generating N-numbered delayed data signals obtained by delaying a phase of the data signal in units of 90/N, where N is a natural number that is not less than 1. In response to a phas... | 08/16/2011 |
| 7944263 | Timing generator and semiconductor test apparatus A timing generator reduces operation-dependent power consumption (AC component) and noises generated from a clock distribution circuit itself in distributing a clock, and further reduces a skew attributed to the clock distribution. A clock distribution circuit 20... | 05/17/2011 |
| 7932765 | Digital delay lines Some embodiments provide real-time variable delays in a delay line. In some of these embodiments, the real-time variable delays may be enable without producing clock glitches. In an embodiment, delay cells in a delay line may be coupled together in a chain to form a... | 04/26/2011 |
| 7525363 | Delay line and delay lock loop A delay line comprises first and second delay arrays and a multiplexer. The first delay array receives a clock signal and a delay control signal, and delays the clock signal to output a first delay array clock signal according to the delay control signal. The second... | 04/28/2009 |
| 7432753 | Delay circuit and semiconductor device A delay circuit comprises: N-stage circuits having a first circuit to an N-th circuit connected in cascade, the input signal being input to the first circuit and a transmission signal delayed by a (k-1)-stage (where 2≦k≦N) circuit is input to a k-th circuit for ... | 10/07/2008 |
| 7427940 | Time-to-digital converter with non-inverting buffers, transmission gates and non-linearity corrector, SOC including such converter and method of phase detection for use in synthesizing a clock signal A time-to-digital converter (TDC), a system-on-chip including a TDC, a method of phase detection for use in synthesizing a clock signal and a non-linearity corrector for a TDC. In one embodiment, the TDC includes a chain of delay elements configured to receive a clo... | 09/23/2008 |
| 7411437 | Triggering events at fractions of a clock cycle Generally, the embodiments presented are directed to circuits and methods for triggering an event at a fraction of a clock cycle. A triggering circuit can comprise two or more input circuits that output an event signal. The event signal is received by one of two or ... | 08/12/2008 |
| 7403056 | Delay apparatus and method thereof The present invention provides a delay apparatus for delaying an input signal by a predetermined delay amount, including: a plurality of delay units for respectively delaying the input signal by the predetermined delay amount, each delay unit having a plurality of d... | 07/22/2008 |
| 7394301 | System and method for dynamically varying a clock signal According to at least one embodiment, a system comprises means for performing an operation utilizing a clock signal. The system further comprises means for supplying a variable operating voltage to the performing means, and means for dynamically varying the frequenc... | 07/01/2008 |
| 7373571 | Achieving desired synchronization at sequential elements while testing integrated circuits using sequential scan techniques A programmable delay circuit is provided in either data input path or a clock input path of a sequential element contained in a scan chain of an integrated circuit. The scan chain is used to test the integrated circuit using a sequential scan technique (e.g., Automa... | 05/13/2008 |
| 7373538 | Method for determining interconnect line performance within an integrated circuit A method for determining propagation delay differences for conductive lines of an integrated circuit is described. A first path is formed by coupling a first portion of conductive lines together. The first portion is associated with a first region of the integrated ... | 05/13/2008 |
| 7358785 | Apparatus and method for extracting a maximum pulse width of a pulse width limiter An apparatus and method for extracting a maximum pulse width of a pulse width limiter are provided. The apparatus and method of the illustrative embodiments performs such extraction using a circuit that is configured to eliminate the majority of the delay cells util... | 04/15/2008 |
| 7332950 | DLL measure initialization circuit for high frequency operation A memory device, delay lock loop circuit (DLL) and DLL reset circuitry are described. The DLL includes a shift register and a measured delay for pre-loading the shift register. The reset circuitry selectively filters a clock signal propagation through the measured d... | 02/19/2008 |
| 7333527 | EMI reduction using tunable delay lines The clock signal is the dominant source of electromagnetic interference (EMI) for many digital electronic devices. EMI generated by these electronic devices must be suppressed to avoid interference with other electronic devices and to satisfy FCC regulations. The pr... | 02/19/2008 |
| 7315219 | Multiphase voltage controlled oscillator A multiphase voltage controlled oscillator includes at least one ring oscillating unit and a resistor ring; the ring oscillating unit is formed by connecting a plurality of phase-delay elements in cascade and the resistor ring is formed by connecting a plurality of ... | 01/01/2008 |
| 7307483 | Electronic oscillators having a plurality of phased outputs and such oscillators with phase-setting and phase-reversal capability Disclosed are multiphase oscillators comprising a plurality of delay stages serially coupled in a loop by a plurality of nodes, with the loop being folded to provide two concentric rings of delay stages with equal numbers of allocated nodes. A second plurality of ne... | 12/11/2007 |
| 7304522 | Spread spectrum clock generator A spread spectrum clock generator includes a plurality of delay cells, wherein each delay cell includes at least one delayer receiving an external clock signal and causing a predetermined propagation delay to the received clock signal, and a controller transmitting ... | 12/04/2007 |
| 7293209 | Split L2 latch with glitch free programmable delay A programmable delay circuit that delays the C2 clock signal by a variable amount that allows the output from the L1 latch to be captured even when there is a large delta between the L1 latch and its L2 latch. This allows the C2 si... | 11/06/2007 |
| 7292175 | Method of testing A/D converter circuit and A/D converter circuit For testing an A/D converter circuit including a pulse delay circuit constituted by a plurality of cascade-connected delay units, and an encoding circuit configured to count the number of the delay units through which the input pulse signal passes within a predeterm... | 11/06/2007 |
| 7292086 | Delay circuit and semiconductor device A delay circuit comprises: N-stage circuits having a first circit to a N-th circuit connected in cascade, the input signal being input to the first circuit and a transmission signal delayed by a (k-1)-stage (where 2≦k≦N) circuit is input to a k-th circuit for se... | 11/06/2007 |
| 7274223 | Semiconductor device As devices are often different in the characteristics from one another, semiconductor chips based on the devices have discrepancies in the performance. A semiconductor device having a semiconductor switching element and a drive controlling means (1) for gener... | 09/25/2007 |
| 7275011 | Method and apparatus for monitoring integrated circuit temperature through deterministic path delays An apparatus for monitoring the temperature of an integrated circuit device includes a conductive wiring pattern formed on the integrated circuit device, extending into areas of the device to be monitored. A deterministic signal source is configured to generate a de... | 09/25/2007 |
| 7268605 | Technique for operating a delay circuit A technique for operating a delay circuit is disclosed. In one particular exemplary embodiment, the technique may be realized by a delay circuit comprising a plurality of data paths. The delay circuit may receive a signal. The delay circuit may also stagger transmis... | 09/11/2007 |
| 7263117 | Dual control analog delay element and related delay method A delay line including analog delay elements each having a selectively adjusted coarse and fine delay portion is described. The coarse delay portion receives an input clock signal and generates a ramp signal having a slope based on a predetermined coarse delay setti... | 08/28/2007 |
| 7257727 | Timer systems and methods Systems and methods are disclosed for timer architectures. For example, in accordance with an embodiment of the present invention, a timer system includes a prescaler and one or more timer cells each having a multiplexer and a counter. ... | 08/14/2007 |
| 7248197 | A/D converter that is implemented using only digital circuit components and digital signal processing A TAD (time analog/digital) type of A/D converter has plural series-connected delay units each producing a delay in accordance with the level of a converter input voltage, with a first-stage delay unit receiving a pulse signal at commencement of each A/D conversion ... | 07/24/2007 |
| 7248125 | Poly-phase VCO with rail to rail output voltage swing and duty cycle control across tuning range An even number phase ring oscillator having at least eight, equally spaced phases. The oscillator includes at least eight stages, defining at least four pairs of stages, with each pair including a first stage and an associated second stage. The first stages are arra... | 07/24/2007 |
| 7240263 | Apparatus for performing stuck fault testings within an integrated circuit An apparatus for performing stuck fault testings within an integrated circuit is disclosed. A delay chain structure includes a first select register, a second select register, a decoder and a chain of multiplexors. With a set of select signals, the first select regi... | 07/03/2007 |
| 7236034 | Self correcting scheme to match pull up and pull down devices The self correcting scheme to match pull up and pull down devices includes: a first comparator for comparing a common mode signal to a high reference limit; a second comparator for comparing the common mode signal to a low reference limit; a first flip flop having a... | 06/26/2007 |
| 7233185 | Vernier circuit for fine control of sample time A vernier time shifting circuit is used for fine-tuning capture of a clock signal and/or a data signal to compensate for fluctuations produced by the system or other variations within non-time invariant parts of the chip. Other variations can include process, temper... | 06/19/2007 |
| 7199631 | Storing an unchanging binary code in an integrated circuit The invention concerns a circuit (1) for storing a binary code (B1, B2, Bi-1, Bi, Bn-1, Bn) in an integrated circuit chip, comprising an input terminal (2) applying a signal (E) triggering reading of the code, output termina... | 04/03/2007 |
| 7196564 | High frequency balanced phase interpolator A phase interpolation system includes an input stage that provides first and second modulated input signals having selected first and second relative phase angles. A weighting system is configured to steer a first portion of the first modulated input signal to an ou... | 03/27/2007 |
| 7188267 | Semiconductor device having a first clock signal configured to operate sychronously with a second clock signal by use of a measuring and setting circuit A first circuit is disposed on the semiconductor substrate, operates synchronously with a first clock signal, and outputs a first output signal delayed by a first delay time from the first clock signal. A first measuring circuit measures indirectly a first increase ... | 03/06/2007 |
| 7181670 | Pipeline architecture for maximum a posteriori (MAP) decoders The sliding window approach to pipeline maximum a posteriori (MAP) decoder architecture is modified to decrease processing time. Once the forward metrics have been calculated for the first sliding window of the decoder, the reverse metrics for each window are calcul... | 02/20/2007 |
| 7178113 | Identification of an integrated circuit from its physical manufacture parameters The invention concerns an identification method and circuit (1) of the network type of parameters contained in an integrated circuit chip, comprising a single input terminal (2) for applying a signal (E) triggering an identification, the output termina... | 02/13/2007 |
| 7173469 | Clocking system and method for a memory A clocking system for a memory that accomplishes these and other objectives has an external clock. A clock shaper has an input coupled to the external clock and an access clock at an output. A first delay block has an input coupled to the external clock and an outpu... | 02/06/2007 |
| 7151397 | Voltage controlled oscillator programmable delay cells A delay cell has selectable numbers of parallel load resistance transistors operable in parallel, and a similarly selectable number of bias current transistors connectable in parallel. The delay cell is preferably differential in construction and operation. A voltag... | 12/19/2006 |
| 7133356 | Method and apparatus for reducing EMI emissions Briefly, in accordance with one embodiment, a circuit to encode binary digital signals so as to reduce EMI emissions during signal transmission across a bus or interconnect includes circuitry to apply a pseudo-random pattern of binary digital signals to encode selec... | 11/07/2006 |
| 7132868 | Semiconductor device As devices are often different in the characteristics from one another, semiconductor chips based on the devices have discrepancies in the performance. A semiconductor device having a semiconductor switching element and a drive controlling means (1) for gener... | 11/07/2006 |
