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| Number | Title | Issue Date |
| 7932764 | Delay circuit with constant time delay independent of temperature variations A delay circuit has: an inverting receiver with a resistive element, the inverting receiver having an input node for receiving an input signal and an output node coupled to the resistive element; a capacitive element, coupled to the output node of the inverting rece... | 04/26/2011 |
| 7444119 | Method for sharing antennas of a wireless device The present invention proposes novel antenna means mounted on handheld devices and methods of use of such antenna means with multiple radios. The novel antenna means exhibit smaller sizes, good performance, have higher reliability, and exhibit novel hardware configu... | 10/28/2008 |
| 7397292 | Digital input buffer with glitch suppression A delay and deglitching circuit suppresses glitches occurring in a received digital signal while introducing a predetermined delay to the signal. The deglitching circuit comprises an RC filter and a Schmitt trigger. A node at the input of the Schmitt trigger fed by ... | 07/08/2008 |
| 7068089 | Digitally programmable I/Q phase offset compensation Delays are produced in differential signals using a variable capacitance provided by MOS varactors coupled between the differential signals. The capacitance values of the MOS varactors is controlled by a bias voltage applied to the bodies of the varactors. Selective... | 06/27/2006 |
| 7057435 | Distributed delay-locked-based clock and data recovery systems A clock and data recovery system using a distributed variable delay line is provided. The clock and data recovery system can use a delay-locked loop methodology to align a local clock with an incoming data stream. The variable delay line can include a transmission l... | 06/06/2006 |
| 6987423 | Two port voltage controlled oscillator for use in wireless personal area network synthesizers A voltage controlled oscillator (VCO) for use in a personal area network synthesizer includes a delay cell (100), a first current amplifier (201, 203) for amplifying an input current, a resister capacitor (RC) tuning network (207, 209, 211) for ... | 01/17/2006 |
| 6867628 | Semiconductor memory delay circuit A circuit includes an input for receiving an input signal, a delay chain connected to the input for delaying the input signal, and a circuit configuration connected to the delay chain downstream of the input, the circuit configuration for supplying a voltage to the ... | 03/15/2005 |
| 6472748 | System and method for providing MMIC seal A system and method for maintaining desired circuit component attributes is shown. According to a preferred embodiment, a high frequency circuit component, such as a MMIC, is retained in a circuit using a degradeable material, such as silver filled epoxy,... | 10/29/2002 |
| 6222409 | Variable analog delay line for analog signal processing on a single integrated circuit chip Programmable analog delay line devices for analog signal processing are constructed on a single integrated circuit chip using a switched capacitor storage scheme for short-term storage of the voltage or charge waveform. These devices provide variable maxi... | 04/24/2001 |
| 6147536 | Delay circuit for delaying a high frequency signal and capable of adjusting an effective pulse width A delay circuit is disclosed which includes first level transition unit for receiving an input signal having more than two different logic levels and varying the pulse width of the signal, and second level transition unit connected with the first level tr... | 11/14/2000 |
| 6097231 | CMOS RC equivalent delay circuit An RC equivalent delay circuit includes an input node, an output node, a feedback node, and an intermediate node; a first inverter having an input coupled to the input node and an output coupled to the intermediate node; a second inverter having an input ... | 08/01/2000 |
| 5990721 | High-speed synchronous clock generated by standing wave A clock for digital devices. Ordinarily, when multiple digital devices are clocked by a common clock, the clock signals frequently arrive at the digital devices at different times, due to propagation delays. The devices are thus not clocked synchronously.... | 11/23/1999 |
| 5936475 | High-speed ring oscillator A ring oscillator comprising a cascade connection of two or several delay stages (31 to 33), wherein each delay stage comprises two differential pairs of two transistors (Q1, Q2; Q3, Q4; Q5, Q7). In the ring oscillator, the collector resistors and the emi... | 08/10/1999 |
| 5896054 | Clock driver A clock driver circuit (100) comprises an input (102) for a reference clock signal. A filter (106) is connected to the input to receive the reference signal and output a filtered signal. A complementary FET driver circuit (108) having a cross-over thresho... | 04/20/1999 |
| 5869996 | Semiconductor composite element, and method of detecting abnormal conditions in an inverter device having the element A semiconductor composite element in which abnormal conditions of overcurrent, control supply voltage reduction and overheat are detected, and different abnormality signals are outputted according to the respective abnormal conditions thus detected. The s... | 02/09/1999 |
| 5497105 | Programmable output pad with circuitry for reducing ground bounce noise and power supply noise and method therefor A programmable output pad is disclosed that reduces ground bounce noise and power supply noise under different power supply values and under different load conditions. The programmable output pad comprises a pre-driver, a driver, and a controllable delay.... | 03/05/1996 |
