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...that the first rickshaw was invented in 1869 by an American Baptist minister, the Rev. E. Jonathan Scobie, to transport his invalid wife around the streets of Yokohama?
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| Number | Title | Issue Date |
| 7990197 | Internal clock driver circuit An internal clock signal driver circuit includes a delay block that delays a rising clock signal and a falling clock signal, and outputs a delayed rising clock signal and a delayed falling clock signal, a rising DLL clock signal generating block that receives and co... | 08/02/2011 |
| 7911250 | Delay circuit A delay circuit includes a ring oscillator and a control circuit. The control circuit includes an edge detector that outputs a first control signal in response to a rising edge or a falling edge of an input signal, and a counter that counts the number of pulses of a... | 03/22/2011 |
| 7893746 | High speed intra-pair de-skew circuit For differential signal transmission (especially in high speed applications), intra-pair skew between paths carrying complementary portions of a differential signal can significantly affect performance. Conventional de-skew circuits employ simple filters (i.e., low-... | 02/22/2011 |
| 7652514 | Internal clock driver circuit An internal clock signal driver circuit includes a delay block that delays a rising clock signal and a falling clock signal, and outputs a delayed rising clock signal and a delayed falling clock signal, a rising DLL clock signal generating block that receives and co... | 01/26/2010 |
| 7586351 | Apparatus and method for controlling delay of signal An apparatus, includes a counter which counts a frequency of input of a first signal, a delay controller which generates a second signal by adding a delay to the first signal, the delay corresponding to the frequency, and a control circuit which halts the counter co... | 09/08/2009 |
| 7560968 | Output driver capable of controlling a short circuit current An output driver capable of controlling a short circuit current includes a driving unit and a driving control unit. The driving unit receives a first driving signal and a second driving signal in response to a control signal and generates an output signal. The drivi... | 07/14/2009 |
| 7421607 | Method and apparatus for providing symmetrical output data for a double data rate DRAM An apparatus and method is disclosed to compensate for skew and asymmetry of a locally processed system clock used to synchronize an output signal, e.g., a data signal or a timing signal, from a logic circuit, for example a memory device. A first phase detector, arr... | 09/02/2008 |
| 7400555 | Built in self test circuit for measuring total timing uncertainty in a digital data path A circuit for measuring timing uncertainty in a clocked digital path and in particular, the number of logic stages completed in any clock cycle. A local clock buffer receives a global clock and provides a complementary pair of local clocks. A first local (launch) cl... | 07/15/2008 |
| 7394300 | Adjustable delay cells and delay lines including the same Delay lines include an adjustable delay cell that adjusts a speed at which an input signal to the adjustable delay cell is transmitted through the adjustable delay cell responsive to a control signal. A plurality of set delay cells are coupled in series with the adj... | 07/01/2008 |
| 7388442 | Digitally controlled oscillator for reduced power over process variations This disclosure relates to a cell-placeable variable-frequency digitally controlled oscillator (DCO) that consumes approximately the same current in a fast process corner as in the case of a slow process corner. By modulating the effective channel length of transist... | 06/17/2008 |
| 7385543 | Systems and methods for asynchronous triggering of an arbitrary waveform generator A system and method for asynchronous triggering in a waveform generator comprising a DAC sample clock for generating DAC sample clock signal. The system includes a sequencer clock for generating a sequencer clock signal having a frequency of 1/N of the DAC sample cl... | 06/10/2008 |
| 7382171 | Semiconductor circuit for detecting a signal propagation time There is provided a semiconductor circuit including three or more nodes at least including one input node and one output node, plural paths which are connected between the three or more nodes and whose signal propagation directions between the nodes are regulated, a... | 06/03/2008 |
| 7378892 | Device for setting a clock delay A device for setting a clock delay is proposed, wherein delayed output clock signals are generated with the aid of delaying means by delaying an input clock signal. The delaying means are configured to provide several differently delayed clock signals simultaneously... | 05/27/2008 |
| 7378891 | Measure-controlled circuit with frequency control Some embodiments include a delay locked circuit having multiple paths. A first path measures a timing of a first clock signal during a measurement. A second path generates a second clock signal based on the first clock signal. The delay locked circuit periodically p... | 05/27/2008 |
| 7365582 | Bootstrapped charge pump driver in a phase-lock loop A charge pump includes first and second pairs of differential transistors. Each transistor includes control, first, and second terminals. First and second charge pump drivers communicate with the control terminal of one of the first pair of differential transistors ... | 04/29/2008 |
| 7355465 | Delay circuit with accurate time to frequency conversion A delay circuit comprises a signal generator and a delay component. The signal generator comprises a terminal for receiving a trigger signal and an output for outputting a signal when receiving a trigger signal with a pre-determined characteristic. The delay mean co... | 04/08/2008 |
| 7348821 | Programmable high-resolution timing jitter injectors high-resolution timing jitter injectors A device includes a first circuit having rows and columns of delay cells to generate delayed signals based on an input signal. The delayed signals are selectable and have a different delay from one another with respect to the input signal. The device is programmable... | 03/25/2008 |
| 7333150 | Method, system, and program product for eliminating error contribution from production switchers with internal DVEs Measurement of the relative timing between images and associated information, for example video and audio. Image mutual event characteristics are recognized in the images and associated mutual event characteristics are recognized in the associated information. The i... | 02/19/2008 |
| 7328115 | Quality assurance IC having clock trimmer A quality assurance integrated circuit for a print controller is provided. The IC has a memory, a system clock having a ring oscillator for generating a clock signal, clock trim circuitry for trimming the clock signal generated by the system clock and a processor. T... | 02/05/2008 |
| 7328377 | Error correction for programmable logic integrated circuits Systems and methods for detecting and correcting errors in programmable logic ICs are provided. In one embodiment, a scrubber periodically reads the memory cells in a programmable logic IC, detects and corrects any errors, and writes the corrected contents back into... | 02/05/2008 |
| 7310757 | Error detection on programmable logic resources Error detection circuitry is provided on a programmable logic resource. Programmable logic resource configuration data is loaded into a cyclic redundancy check (CRC) module where a checksum calculation may be performed. In one embodiment, the checksum may be compare... | 12/18/2007 |
| 7295055 | Device for eliminating clock signal noise in a semiconductor integrated circuit A semiconductor integrated circuit includes a integration circuit which has a first integrating portion and a second integrating portion. The semiconductor integrated circuit also includes a data input portion, data processing portion and data output portion. A cloc... | 11/13/2007 |
| 7295054 | Buffer capable of controlling slew rate in drive IC The present invention relates generally to a buffer of a drive Integrated Circuit (IC) and, more particularly, to a buffer of a drive IC for driving a spatial light modulator that can meet a desired dynamic slew rate characteristic by controlling current that affect... | 11/13/2007 |
| 7288978 | Delay circuit and ring oscillator using the same In a delay circuit, when a first conductivity-type transistor (M6) becomes conductive on the basis of one level of its input signal, a first current path is formed through a source side transistor (M4), the first conductivity-type transistor (M6... | 10/30/2007 |
| 7274237 | Measure control delay and method having latching circuit integral with delay circuit A measure control delay includes a measuring delay line and a signal generating delay line, each of which include a plurality of series-connected delay units. A digital signal is applied to an initial delay unit in the measuring delay line and it sequentially propag... | 09/25/2007 |
| 7271638 | Delay circuit and delay synchronization loop device A delay circuit includes a first delay line circuit having a plurality of stages of delay units, a second delay line circuit having a plurality of stages of delay units, a plurality of transfer circuits provided in association with respective stages of the delay uni... | 09/18/2007 |
| 7268605 | Technique for operating a delay circuit A technique for operating a delay circuit is disclosed. In one particular exemplary embodiment, the technique may be realized by a delay circuit comprising a plurality of data paths. The delay circuit may receive a signal. The delay circuit may also stagger transmis... | 09/11/2007 |
| 7263117 | Dual control analog delay element and related delay method A delay line including analog delay elements each having a selectively adjusted coarse and fine delay portion is described. The coarse delay portion receives an input clock signal and generates a ramp signal having a slope based on a predetermined coarse delay setti... | 08/28/2007 |
| 7259608 | System and method for open-loop synthesis of output clock signals having a selected phase relative to an input clock signal Delay circuits are used in a manner similar to a synchronized mirror delay circuit to generate a quadrature clock signal from an input clock signal. The input clock signal is coupled through a series of first delay circuit for one-half the period of the input clock ... | 08/21/2007 |
| 7253672 | System and method for reduced power open-loop synthesis of output clock signals having a selected phase relative to an input clock signal A signal generating circuit includes a pulse generator generating a pulse responsive to a periodic clock reference signal. The pulse propagates through a plurality of series-connected delay elements in a measurement delay line. The measurement delay line is coupled ... | 08/07/2007 |
| 7230495 | Phase-locked loop circuits with reduced lock time PLL circuits are provided in which a voltage-controlled oscillator (VCO) comprising one or more voltage-controlled delay units (VCDs) is initialized with the control voltage of a voltage-controlled delay line (VCDL) having substantially identical VCDs. In general, V... | 06/12/2007 |
| 7230467 | Constant edge generation circuits and methods and systems using the same A circuit for generating stable signal edges includes an output driver circuit having a current path for varying a charge on a capacitor in response to an input signal and constant current generation circuitry for maintaining a constant current through the current p... | 06/12/2007 |
| 7227485 | Waveform control circuit The waveform conform control circuit includes a waveform generator, an amplitude adjustment device and an offset device. The waveform generator produces a current waveform. The amplitude adjustment device receives amplitudes amplitude data and produces a predetermin... | 06/05/2007 |
| 7227809 | Clock generator having a delay locked loop and duty cycle correction circuit in a parallel configuration A clock generator having a delay locked loop and a duty cycle correction circuit. The delay locked loop adjusts a first adjustable delay circuit to generate a first output clock signal that is synchronized with a first input clock signal and adjusts a second adjusta... | 06/05/2007 |
| 7224186 | Semiconductor circuit device The present invention relates to a semiconductor circuit device including a logic circuit and a signal line driving circuit. The logic circuit is operated at high supply voltage and outputs a signal with a high voltage amplitude. The signal line driving circuit rece... | 05/29/2007 |
| 7212057 | Measure-controlled circuit with frequency control A delay locked circuit has multiple paths for receiving an external signal. One path measures a timing of the external signal during a measurement. Another path generates an internal signal based on the external signal. The delay locked circuit periodically performs... | 05/01/2007 |
| 7202725 | Delay control circuit device, and a semiconductor integrated circuit device and a delay control method using said delay control circuit device By forming adjacent wiring 4 adjacent to signal wiring 3 and using a control circuit 13 comprising a 2-input NAND 20 circuit or the like to input a signal S4 corresponding to a signal S3 in the signal wiring 3 to the ... | 04/10/2007 |
| 7157951 | Digital clock manager capacitive trim unit A delay line for a digital clock manager includes a tap delay structure and a trim delay structure. The trim delay structure includes a first buffer coupled to receive a clock signal from the tap delay structure, and in response, provide a delayed clock signal to a ... | 01/02/2007 |
| 7154795 | Clock signal initiated precharge technique for active memory subarrays in dynamic random access memory (DRAM) devices and other integrated circuit devices incorporating embedded DRAM A precharge initiated dynamic random access memory (DRAM) technique of especial utility with respect to DRAM devices and other integrated circuit devices incorporating embedded DRAM in which the rising edge of each clock initiates a precharge to those subarrays that... | 12/26/2006 |
| 7154320 | Frequency-based slope-adjustment circuit A method and apparatus for a frequency-based slope-adjustment circuit block are described herein. ... | 12/26/2006 |
