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| Number | Title | Issue Date |
| 7911249 | Semiconductor integrated circuit A combinational circuit is connected to a flip-flop circuit. A clock buffer supplies a clock to the flip-flop circuit. A control circuit controls a delay time of the flip-flop circuit and a delay time of the combinational circuit independently. ... | 03/22/2011 |
| 7902897 | Variable delay circuit and delay correction method A variable delay circuit is provided which has a plurality of delay elements. The variable delay circuit comprises a delay time correction circuit for individually correcting a delay time on each of the plurality of delay elements to compensate for the variation in ... | 03/08/2011 |
| 7830191 | Vernier delay circuit A ring oscillator oscillates at a frequency determined by an input bias signal. A bias signal adjusting unit produces a bias signal for the ring oscillator using feedback so that the oscillation frequency of the ring oscillator matches a predetermined reference freq... | 11/09/2010 |
| 7733148 | Temperature independent delay circuits Delay circuits are provided. Some embodiments of delay circuits herein include a delay line including multiple delay cells connected in series and a variable voltage supplier operative to output a voltage value proportional and/or inversely proportional to a tempera... | 06/08/2010 |
| 7696802 | Data delay control circuit and method A data delay control circuit and method that can adaptively reflect changes in an operating environment, such as an operating temperature, an operating voltage and a manufacturing process of a semiconductor chip. The data delay control circuit is designed to be able... | 04/13/2010 |
| 7675339 | System and method for generating a delayed clock signal of an input clock signal A system and method for generating a delayed clock signal of an input clock signal involves selectively delaying the input clock signal to produce the delayed clock signal based on the duty cycle of the input clock signal and the duty cycle of a logic signal derived... | 03/09/2010 |
| 7570096 | Direct digital synthesizer with variable reference for improved spurious performance Improvement of quantization errors that arise in a delay line with finite resolution. A direct digital synthesizer (DDS), which contains a numerically controlled oscillator (NCO) and a digital-to-phase converter (DPC), is placed in the feedback loop of a phase locke... | 08/04/2009 |
| 7498859 | Driving device using CMOS inverter A driving device using a CMOS inverter performs a stable operation by using a compensating circuit to compensate variation widths when the process condition or external environment is changed. The driving device comprises a power regulating unit for regulating a dri... | 03/03/2009 |
| 7453302 | Temperature compensated delay signals A temperature compensated delay circuit for delaying a signal within an integrated circuit includes a temperature sensor. The temperature sensor is configured to sense a temperature proximal to the integrated circuit and configured to provide a control signal repres... | 11/18/2008 |
| 7436235 | Digital clock modulator A digital clock modulator provides a smoothly modulated clock period to reduce emitted electro-magnetic radiation (EMR). The digital clock modulator includes a plurality of delay elements connected in series and receiving as an input an unmodulated clock signal. A m... | 10/14/2008 |
| 7411436 | Self-timed thermally-aware circuits and methods of use thereof Apparatus and methods for regulating gate delays of synchronous and asynchronous digital circuits. Thermally-sensitive circuits include, generally, temperature sensitive voltage sources outputting a voltage signal indicative of the temperature of the digital circuit... | 08/12/2008 |
| 7394301 | System and method for dynamically varying a clock signal According to at least one embodiment, a system comprises means for performing an operation utilizing a clock signal. The system further comprises means for supplying a variable operating voltage to the performing means, and means for dynamically varying the frequenc... | 07/01/2008 |
| 7368967 | Timing controller and controlled delay circuit for controlling timing or delay time of a signal by changing phase thereof A controlled delay circuit has a first gate chain, and a second gate chain. The first gate chain is used to measure a time difference between a changeover point of a first control signal and a changeover point of a second control signal. The second gate chain, which... | 05/06/2008 |
| 7362061 | Gate driver, motor driving device including the gate driver, and apparatus equipped with the motor driving device A gate driver for forcing a power transistor including a gate electrode insulated with oxide film into conduction or shut-off, the gate driver includes a first current source for outputting a first current value to raise an electric potential of the gate electrode f... | 04/22/2008 |
| 7362151 | Timing circuits with improved power supply jitter isolation technical background In accordance with the invention, feed forward compensation of jitter induced by power supply noise is incorporated into the negative feedback control loop of a timing synchronization circuit, such as a phase locked loop or delay locked loop. More particularly, the ... | 04/22/2008 |
| 7355435 | On-chip detection of power supply vulnerabilities On-chip sensor to detect power supply vulnerabilities. The on-chip sensor employs a sensitive delay chain and an insensitive delay chain to detect power supply undershoots and overshoots without requiring external off-chip components. Undershoots and overshoots outs... | 04/08/2008 |
| 7356785 | Optimizing IC clock structures by minimizing clock uncertainty A process is provided for optimizing a clock net in the form of a tree having a root defined by a driver pin and a plurality of leaves defined by driven pins. The process includes forcing a first buffer to a center of gravity of the plurality of leaves, inserting a ... | 04/08/2008 |
| 7353420 | Circuit and method for generating programmable clock signals with minimum skew A programmable clock deskewer generates an output clock with minimal clock skew. This is accomplished by means of a single series path coupling the input clock to the output clock. The programmable clock deskewer includes: an output clock generator, responsive to th... | 04/01/2008 |
| 7323921 | Clock generator, system on a chip integrated circuit and methods for use therewith A system on a chip integrated circuit includes a first circuit module and N other circuit modules that are operable to produce at least one output signal based on at least one input signal. A reference oscillator for generating a base clock signal for the first circ... | 01/29/2008 |
| 7312666 | PLL circuit configured to distribute its loop control signal to CDR circuits A semiconductor integrated circuit includes a phase-locked loop (PLL) circuit configured to generate an oscillation output signal synchronized with a reference clock and a plurality of clock and data recovery (CDR) circuits configured to adjust a phase of the oscill... | 12/25/2007 |
| 7301186 | Metal oxide semiconductor transistor and method for manufacturing the same A metal oxide semiconductor (MOS) transistor includes a source region having at least one source contact; a drain region having at least one drain contact; and a gate provided between the source region and the drain region, wherein the number of source contacts incl... | 11/27/2007 |
| 7295489 | Method and circuit for writing double data rate (DDR) sampled data in a memory device A method and circuit for sampling and writing data in a double data rate (DDR) memory device, capable of securing sufficient setup and hold margins regardless of the operation frequency. Transferring first and second sampled input data to a first path using a first ... | 11/13/2007 |
| 7292079 | DLL-based programmable clock generator using a threshold-trigger delay element circuit and a circular edge combiner A DLL-based programmable clock generator using a threshold-trigger delay element and an edge combiner is proposed. A threshold-trigger delay element with full swing complementary output signals consumes no dc power. It exhibits small delay error resulting reduced ou... | 11/06/2007 |
| 7292085 | Timing delay generator and method using temperature stabilisation A timing delay generator for supplying a signal delayed by a predetermined period comprises a vernier that provides variable delays for a main signal, the delays being sensitive to temperature variation, a sensor for sensing the vernier's temperature and a feedback ... | 11/06/2007 |
| 7288978 | Delay circuit and ring oscillator using the same In a delay circuit, when a first conductivity-type transistor (M6) becomes conductive on the basis of one level of its input signal, a first current path is formed through a source side transistor (M4), the first conductivity-type transistor (M6... | 10/30/2007 |
| 7287143 | Synchronous memory device having advanced data align circuit A semiconductor device for performing an N-bit prefetch operation, N being a positive integer includes a data strobe buffering means for generating N number of align control signals based on a data strobe signal and a external clock signal; a receiving block in resp... | 10/23/2007 |
| 7285988 | Comparator circuit with offset control A semiconductor integrated circuit has: a differential amplifier circuit including a first MOS transistor connected between a first node and a common node and a second MOS transistor connected between a second node and the common n... | 10/23/2007 |
| 7279954 | On-chip temperature detection device An on-chip temperature detection device includes: a bipolar type power transistor; a mirror transistor in which a collector current, which is proportional to a collector current of the power transistor, flows; a current detection section that detects the collector c... | 10/09/2007 |
| 7276950 | Prevention of the propagation of jitters in a clock delay circuit The clock delay circuit according to the present invention includes a delay circuit section, a selection circuit section, and jitter suppression elements. The delay circuit section provides a plurality of delay clock signals that are obtained by delaying a clock sig... | 10/02/2007 |
| 7274236 | Variable delay line with multiple hierarchy Disclosed herein are improved, simplified designs for a hierarchical delay line (HDL). The HDL is useful in providing precise phase control between an input clock signal and an output clock signal, and has particular utility as the variable delay in a delay-locked l... | 09/25/2007 |
| 7274246 | Switching circuit using multiple common-drain JFETs for good heat dissipation capability and small PCB layout area A switching circuit uses multiple common-drain JFETs to serve as the low-side switches of the switching circuit, and each of the low-side JFET is coupled between a high-side switch and a power node. Since a JFET can endure high voltage at both drain side and source ... | 09/25/2007 |
| 7272526 | Method and apparatus for autocalibrating a plurality of phase-delayed clock signal edges within a reference clock period An apparatus for measuring the time delay between adjacent clock edges includes target and delay signal paths, a variable delay module in said delay signal path, the delay cell having a delay bias input, and a phase detector having respective inputs coupled to the t... | 09/18/2007 |
| 7272742 | Method and apparatus for improving output skew for synchronous integrated circuits A method and apparatus for improving output skew across the data bus of a synchronous integrated circuit device. The device includes a clock input buffer that receives a system clock signal and generates a buffered clock signal, a delay line that receives the buffer... | 09/18/2007 |
| 7268589 | Address transition detector for fast flash memory device An address transition detector circuit includes an input node, an output node, a bandgap reference node, and Pbias and Nbias nodes having voltages derived from the bandgap reference node. First through fifth cascaded inverters are each powered ... | 09/11/2007 |
| 7263117 | Dual control analog delay element and related delay method A delay line including analog delay elements each having a selectively adjusted coarse and fine delay portion is described. The coarse delay portion receives an input clock signal and generates a ramp signal having a slope based on a predetermined coarse delay setti... | 08/28/2007 |
| 7260375 | Frequency agile RF circuit A frequency agile sequential amplifier circuit that includes first and second RF amplifiers coupled by a SAW delay line, a double balanced mixer coupling the first RF amplifier to the SAW delay line, the output of the first RF amplifier providing a signal as a first... | 08/21/2007 |
| 7256617 | Method and apparatus to linearize output buffer and on-chip termination A driver circuit that outputs a data signal uses feedback of the data signal to the driver circuit to modulate a drive strength of the driver circuit. The driver circuit has a pull-up driver stage and a pull-down driver stage. The pull-up driver stage uses a pull-up... | 08/14/2007 |
| 7253672 | System and method for reduced power open-loop synthesis of output clock signals having a selected phase relative to an input clock signal A signal generating circuit includes a pulse generator generating a pulse responsive to a periodic clock reference signal. The pulse propagates through a plurality of series-connected delay elements in a measurement delay line. The measurement delay line is coupled ... | 08/07/2007 |
| 7248091 | Semiconductor device having delay drift compensation circuit that compensates for delay drift caused by temperature and voltage variations in clock tree A semiconductor device having a delay drift compensation circuit that compensates for a delay drift caused by temperature and voltage variations in a clock tree includes a clock driver having an output port, a first circuit having an input port, a first signal path ... | 07/24/2007 |
| 7236033 | System and method for detecting processing speed of integrated circuit A system for detecting the processing speed of an integrated circuit (IC) includes a flip-flop, a delay module, and a judge unit. The flip-flop receives a clock signal as a trigger signal and generates an inverted output signal. The delay module receives the inverte... | 06/26/2007 |
