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| Number | Title | Issue Date |
| 8174300 | Clock generator, pulse generator utilizing the clock generator, and methods thereof A clock generator for generating a target clock signal, comprising: a control circuit, receiving a reference clock signal, and for generating a clock enable signal and a delay selecting signal according to the reference clock signal; a delay module, coupled to the c... | 05/08/2012 |
| 8120408 | Voltage controlled oscillator delay cell and method A delay cell circuit (200) is disclosed. The delay cell circuit may include a differential stage (202) and a cross-coupled stage (204). The cross-coupled stage can include resistors (210-0 and 210-1) the function to r... | 02/21/2012 |
| 8115532 | Linear monotonic delay chain circuit A method and circuit for generating an adjustable delay signal is presented, wherein the delay can be linear and monotonic with high resolution delay steps. The circuit utilizes one or more serially coupled delay cells and a load cell. Each delay cell comprises an i... | 02/14/2012 |
| 8058919 | Delay circuit A delay circuit with a delay time being more accurate and a circuit area being reduced is provided. The delay circuit includes a resistance element 3, a capacitor element 4 and a connection wiring 6. The connection wiring 6 includes a fir... | 11/15/2011 |
| 8044696 | Delay circuit having long delay time and semiconductor device comprising the same A delay circuit has a long delay time and a semiconductor device includes the delay circuit. The delay circuit includes an inverter circuit unit having at least one inverter. Each of the inverters includes a first transistor connected to a supply voltage and a secon... | 10/25/2011 |
| 8013654 | Clock generator, pulse generator utilizing the clock generator, and methods thereof A clock generator for generating a first target clock signal includes: a control circuit, receiving a reference clock signal, and for generating a first clock enable signal and a first delay selecting signal according to the reference clock signal; a first clock gat... | 09/06/2011 |
| 7973582 | Timing control circuit and semiconductor storage device Disclosed is a timing control circuit which receives a first clock having a period T1 and a group of second clocks of L different phases (where L is a positive integer) spaced apart from each other at substantially equal intervals and which generates a fine t... | 07/05/2011 |
| 7969220 | Delay circuit A delay circuit includes first and second selective delay stages each including a number of unit delay cells to delay signals applied thereto; and a delay control unit configured to control selectively applying an input signal to the first selective delay stage or t... | 06/28/2011 |
| 7965120 | Digitally controlled CML buffer Techniques and corresponding circuits for achieving programmable delay of a current mode logic delay buffer are provided. The techniques provide for incremental delay with substantially equal increments. Delay may be achieved through the use of a circuit arrangement... | 06/21/2011 |
| 7952410 | Semiconductor device and voltage-controlled oscillation circuit A voltage-controlled oscillation circuit (15) includes a plurality of independent ring oscillation circuits different in the number of stages; and a selector (22) selectively outputting as a feedback clock signal (FB) an output of one of the ring oscil... | 05/31/2011 |
| 7928790 | Integrated circuit and programmable delay Integrated circuit and programmable delay. One embodiment provides an integrated circuit including a programmable delay element having a plurality of single delay cells. The delay cells include a first input and a second input and a first output. The delay cells are... | 04/19/2011 |
| 7868679 | Circuit, method for receiving a signal, and use of a random event generator A circuit is provided that includes an input for a clock signal, a random event generator for outputting a random signal, in particular random numbers, a settable delay device that is connected to the input for the clock signal and is connected to the random event g... | 01/11/2011 |
| 7859318 | Delay line regulation using high-frequency micro-regulators A regulated delay line device includes main regulator coupled to a node, and a plurality of delay branches coupled to the node to receive a voltage output to the node by the main regulator. Each of the plurality of delay branches includes a micro-regulator and a del... | 12/28/2010 |
| 7795942 | Stage by stage delay current-summing slew rate controller A stage by stage delay current-summing slew rate controller includes a delay controller, a delay cell array, a current source array, a switch array, a load. The delay cell array includes N delay cells, the switch array includes N switches, and the switch includes N ... | 09/14/2010 |
| 7795941 | Frame pulse signal latch circuit and phase adjustment method A frame pulse signal latch circuit has: a pulse-width expanding unit which outputs a frame pulse signal FPIN having a pulse width longer than a m-clock cycle; a phase adjustment unit which generates a phase-adjusted output clock CLKâ²; a flip-flop which latches the... | 09/14/2010 |
| 7777544 | System and method to detect order and linearity of signals A method comprises applying a first delay to a first signal that is ahead of a second signal in a series of signals and determining a first number of delay units that provides the first delay to change an order between the delayed first signal and the second signal ... | 08/17/2010 |
| 7772908 | Voltage and temperature compensation delay system and method A delay circuit provides a voltage and temperature compensated delayed output signal. The delay circuit includes a first delay stage that receives an input signal, and generates a delayed output signal from the input signal. The delay circuit also includes a second ... | 08/10/2010 |
| 7759998 | Timing adjustment circuit Three flip-flops receive a common data signal input through a data terminal based on different timing signals which are obtained from an external timing signal and differ from one another by a specific delay step. A judging circuit judges whether or not the output d... | 07/20/2010 |
| 7746141 | Delay circuit A delay circuit includes a delay time setting circuit to set a delay time of an output signal with respect to an input signal, a first transistor connected to an input terminal of the delay time setting circuit and configured to set a first voltage to the input term... | 06/29/2010 |
| 7733147 | Delay circuit of delay locked loop having single and dual delay lines and control method of the same A delay circuit in a delay locked loop includes a first delay circuit unit for delaying an input signal using a single delay line in response to first control signals and then outputting a first delay signal and a second delay signal, and a second delay circuit unit... | 06/08/2010 |
| 7733146 | SET and SEGR resistant delay cell and delay line for Power-On Reset circuit applications A delay line appropriate for use in a POR circuit or other integrated circuit in a space environment combines three separate circuit techniques to improve performance without unnecessarily increasing circuit area or adding to manufacturing costs when compared to a s... | 06/08/2010 |
| 7688126 | Time delay circuit and time to digital converter A time delay circuit is disclosed and includes a delay line with a first delay circuit and at least a second delay circuit connected downstream. An interpolation circuit is used to generate intermediate signals derived by delayed successive signals in the delay line... | 03/30/2010 |
| 7683689 | Delay circuit with delay cells in different orientations A delay circuit that includes a first delay cell oriented in a first orientation and a second delay cell oriented in a second orientation is described. In one embodiment, the first orientation is perpendicular to the second orientation. More specifically, in one emb... | 03/23/2010 |
| 7679414 | Method and apparatus for tuning delay Aspects of the disclosure provide a fine tunable digital delay circuit that can be applied in a high frequency digital circuit. Further, the digital delay circuit can utilize a level restoring technique to enable a wide tunable delay range. The delay circuit can inc... | 03/16/2010 |
| 7633326 | Timing controller and controlled delay circuit for controlling timing or delay time of a signal by changing phase thereof A controlled delay circuit has a first gate chain, and a second gate chain. The first gate chain is used to measure a time difference between a changeover point of a first control signal and a changeover point of a second control signal. The second gate chain, which... | 12/15/2009 |
| 7609103 | Delay circuit with reference pulse generator to reduce variation in delay time A delay circuit to generate and output a delayed signal delayed from an input signal includes a reference pulse generating circuit to generate a reference pulse train in response to the input of the input signal, the reference pulse generating circuit having a feedb... | 10/27/2009 |
| 7605629 | Adjusting circuit and method for delay circuit Disclosed is an adjusting circuit for determining a target delay clock signal of a delay circuit having a plurality of delay units. The delay circuit generates a plurality of delay clock signals, and the adjusting circuit includes: a difference signal generating cir... | 10/20/2009 |
| 7605628 | System for glitch-free delay updates of a standard cell-based programmable delay A method for glitch-free updates of a standard cell-based programmable delay including the steps of (A) generating an output signal in response to an input signal and a plurality of first control signals and (B) generating the plurality of first control signals in r... | 10/20/2009 |
| 7564284 | Time delay circuit and time to digital converter A time delay circuit is disclosed and includes a delay line with a first delay circuit and at least a second delay circuit connected downstream. An interpolation circuit is used to generate intermediate signals derived by delayed successive signals in the delay line... | 07/21/2009 |
| 7557631 | Voltage and temperature compensation delay system and method A delay circuit provides a voltage and temperature compensated delayed output signal. The delay circuit includes a first delay stage that receives an input signal, and generates a delayed output signal from the input signal. The delay circuit also includes a second ... | 07/07/2009 |
| 7551015 | Operating frequency generating method and circuit for switching voltage converter An operating frequency generating method and circuit for a switching voltage converter are provided. The method includes the following steps. First, a reference clock signal and a digital period signal are received. The phase of the digital period signal is delayed ... | 06/23/2009 |
| 7548104 | Delay line with delay cells having improved gain and in built duty cycle control and method thereof A delay line including a sequence of identical delay cells with improved gain and in built duty cycle distortion control and a method thereof is disclosed. Each delay cell of the sequence includes a current source, four transistors, and a load capacitor. A gate of t... | 06/16/2009 |
| 7538594 | Method for reducing delay difference of differential transmission and system thereof The present invention discloses a system and method for reducing delay difference of differential transmission, a certain delay difference between waveforms of the P signal and N signal is generated through controlling delay adjustment to P signal or N signal of the... | 05/26/2009 |
| 7528641 | Delay circuit having a correction circuit The present invention provides a delay circuit in which normal CMOS type inverters and modified inverters added with delay PMOSs on the power supply voltage VDD terminal side are alternately cascade-connected. A correction circuit that supplies a control signal to t... | 05/05/2009 |
| 7518429 | Delay circuit A delay circuit (12) includes a resistor (R1), a capacitor (C), and a discharging circuit (14). The discharging circuit includes a PNP transistor (Q1) and an NPN transistor (Q2). The capacitor has one terminal connected to one term... | 04/14/2009 |
| 7511546 | Synchronous memory device with output driver controlller A synchronous memory device having an output driver controller, comprises a DLL circuit for receiving an external clock and outputting an internal clock; an output driver for outputting data in synchronism with the internal clock; and an output driver controller for... | 03/31/2009 |
| 7508246 | Performance variation compensating circuit and method A circuit's performance may vary based on various factors such as, for example, process, voltage, and/or temperature. In one embodiment, a circuit includes an input terminal which receives an input signal, a delay selection section which delays the input signal by a... | 03/24/2009 |
| 7456670 | Distributed delay-locked-based clock and data recovery systems A clock and data recovery system using a distributed variable delay line is provided. The clock and data recovery system can use a delay-locked loop methodology to align a local clock with an incoming data stream. The variable delay line can include a transmission l... | 11/25/2008 |
| 7446583 | Switching arrangement for interconnecting electrolytic capacitors Switching arrangement for interconnecting electrolytic capacitors that comprises an electronic switch formed by a semiconductor device and a delay member. The semiconductor device has a control input which is, through an RC-type delay member, connected to a control ... | 11/04/2008 |
| 7443254 | Relaxation oscillator with propagation delay compensation for improving the linearity and maximum frequency A tunable oscillator comprises a control supply configured to output a control output operable to tune the tunable oscillator. The tunable oscillator further comprises an oscillator circuit configured to output a signal such that a frequency of the signal increases ... | 10/28/2008 |
