Bizarre Patents
A haircutting appliance comprises an enclosed housing having a hollow handle connecting the housing to a vacuum source to carry away cut hairs from a subject's head.
PatentStorm News
Make the Most of Our Site
See this month's Top Inventors and Most Cited Patents.
Stay on top of the latest innovations by subscribing to an RSS feed.
Registered users: Manage your profile.
| Number | Title | Issue Date |
| 7436233 | Normal mode and green mode pulse width modulation controller A PWM controller that effectively transitions between normal mode and green power mode is disclosed. A driver provides a normal drive signal during normal operation. A pulse width detector detects the pulse width of the PWM signal and if the pulse width drops below ... | 10/14/2008 |
| 7414438 | Clock based voltage deviation detector The clock based voltage deviation detector of the present invention includes a pulse module, an indicator module and a correlation module. The pulse module generates a stream of reset pulses as a function of a clock signal. The indicator module generates a pass/fail... | 08/19/2008 |
| 7378892 | Device for setting a clock delay A device for setting a clock delay is proposed, wherein delayed output clock signals are generated with the aid of delaying means by delaying an input clock signal. The delaying means are configured to provide several differently delayed clock signals simultaneously... | 05/27/2008 |
| 7339403 | Clock error detection circuits, methods, and systems Clock error detections circuits can detect clock duty cycle error and/or quadrature phase error. During an evaluation phase, capacitors are charged. During an evaluation phase, the capacitors are unequally discharged based on the error. A positive feedback mechanism... | 03/04/2008 |
| 7320049 | Detection circuit for mixed asynchronous and synchronous memory operation A memory access mode detection circuit and method for detecting and initiating memory access modes for a memory device The memory access mode detection circuit receives the memory address signals, the control signals, and the clock signal and generates a first mode ... | 01/15/2008 |
| 7266039 | Circuitry and method for adjusting signal length A circuit for adjusting a signal length is adapted for a memory device. The circuit adjusts a signal length of an ATD signal. The circuit includes a timing module, an encoding module and a logical control unit. Wherein, the timing module generates a plurality of tim... | 09/04/2007 |
| 7242219 | Circuit for parity tree structure A circuit for a parity tree is disclosed. In one embodiment, a circuit for a parity tree includes a pull-up circuit, a pull-down circuit, and a cross-couple circuit. The circuit, an XOR/XNOR circuit, includes both an output node and an inverted output node. For a gi... | 07/10/2007 |
| 7227387 | Measuring pulse edge delay value relative to a clock using multiple delay devices to address a memory to access the delay value A pulse width measurement system is provided with components in an FPGA so that pulse widths can be measured that are smaller than the frequency limits of the FPGA system clock. For the measurement, an incoming pulse is fed into the FPGA to many (e.g. 32) I/O inputs... | 06/05/2007 |
| 7200187 | Modulator for digital amplifier A digital modulator for driving a digital amplifier. The digital modulator has a subtractor which receives a digital input signal. A filter amplifier receives the output of the filter amplifier and is tuned to an idle frequency of the digital modulator. The digital ... | 04/03/2007 |
| 7200186 | Methods and apparatus for reducing power usage of a transmitter and receiver coupled via a differential serial data link Methods and apparatus are disclosed for using in-band signal(s) over a differential serial data link to reduce power usage of a transmitter and receiver coupled by the link. ... | 04/03/2007 |
| 7170949 | Methods and apparatus for signaling on a differential link Methods and apparatus are disclosed for transitioning a receiver from a first state to a second state using an in-band signal over a differential serial data link. ... | 01/30/2007 |
| 7142478 | Clock stop detector A clock stop detector for a memory comprises a first switch that closes in response to a first logic level of a clock signal to charge a capacitor, a second switch that closes in response to a second logic level of the clock signal to discharge the capacitor, and a ... | 11/28/2006 |
| 7132868 | Semiconductor device As devices are often different in the characteristics from one another, semiconductor chips based on the devices have discrepancies in the performance. A semiconductor device having a semiconductor switching element and a drive controlling means (1) for gener... | 11/07/2006 |
| 7113606 | Adjustable harmonic distortion detector and method for using the same There is provided an adjustable harmonic distortion detector that includes a clock signal source, means for the detection of a first period of evaluation, and means for the detection of a second period of evaluation. The detector has the characteristic that a first ... | 09/26/2006 |
| 7107474 | Data transfer unit and method A data transfer unit (13) is provided for use in a clock swapping system which controls data transfer with a data transmission permit signal (rwo) and data reception permit signal (rro). The data transfer unit (13) includes a data latch (21) whi... | 09/12/2006 |
| 7106116 | Pulse duty deterioration detection circuit A pulse duty deterioration detection circuit with a high monitoring precision is easily provided. The pulse duty deterioration detection circuit comprises a delay circuit comprised of a general-purpose gate circuit which generates a delayed synchronous to-be-monitor... | 09/12/2006 |
| 7053667 | Single wire digital interface A single-wire digital interface for receiving digital data as a stream of pulses, with ‘1’ and ‘0’ logic levels represented with pulses having “first” and “second” pulse widths, respectively. A low-pass filter produces an output that increases at a k... | 05/30/2006 |
| 7016791 | Particle sizing refinement system A plurality of particle size reference values are specified. Particle size data is obtained based at least in part on the specified plurality of particle size reference values. ... | 03/21/2006 |
| 6970799 | Method and apparatus for particle sizing A method and apparatus provides for particle size detection. A particle detector signal is utilized to provide particle size information. The particle detection signal is obtained by utilizing particle detector information. ... | 11/29/2005 |
| 6952139 | Oscillator and electronic apparatus using the same An oscillator operated with an external power source or an external save power source is provided comprising: a clock signal generation unit for generating and outputting a clock signal; a power-on detection unit for detecting the power-on of the external power sour... | 10/04/2005 |
| 6946880 | Compact balun for rejecting common mode electromagnetic fields A space-efficient broadband balun (20). The balun (20) includes a first mechanism (44, 80, 82, 94, 96) for receiving an input signal (52, 54) having an undesirable component. A second mechanism (50) rejects the undesirable componen... | 09/20/2005 |
| 6940926 | Digital phase/frequency detector A digital phase/frequency detector capable of being implemented with on-chip components and configured to detect signals having small modulation indices. Transition points within the signal are detected and the width between successive transition points measured and... | 09/06/2005 |
| 6753705 | Edge sensitive detection circuit An edge sensitive detection circuit includes a filter module and a soft latch module. The filter module is operably coupled to receive an input logic signal that corresponds to the triggering of an event and produces a pulse signal in response to an edge of the inpu... | 06/22/2004 |
| 6636080 | Apparatus for detecting edges of input signal to execute signal processing on the basis of edge timings An apparatus for detecting an edge timing of an input signal and operating on the basis of the edge timing while power consumption thereof is reduced. The apparatus includes an edge detecting circuit that detects edges of an input signal to generate an ed... | 10/21/2003 |
| 6552578 | Power down circuit detecting duty cycle of input signal When the clock is stopped during a power-down mode, a clock duty-cycle detector asserts a power-down signal. The clock input is filtered to produce an average clock voltage over several clock periods. The average clock voltage is compared to an upper refe... | 04/22/2003 |
| 6483361 | Lock detector for determining phase lock condition in PLL on a period-by-period basis according to desired phase error The lock detector circuit determines and indicates whether the PLL is in an in-lock mode or in an out-of-lock mode without using an external capacitor for controlling phase error. Moreover, the lock detector circuit indicates the operating mode of the PLL... | 11/19/2002 |
| 6389548 | Pulse run-length measurement for HF data signal by dividing accumulated phase difference between first and second zero-crossings by single-cycle range using multiple cycle range sawtooth waveform A system and method for accurately measuring a pulse run length in a high frequency (HF) data signal while utilizing a low analog-to-digital conversion (ADC) sampling rate. Four bits are added to the most significant end of an oscillator's accumulator reg... | 05/14/2002 |
| 6252447 | Edge transition detection circuit with variable impedance delay elements According to the present invention, by setting the logic state of one or more delay signals to appropriate values, the resistive value of a plurality of power supply delay elements throughout an integrated circuit having distributed circuit blocks may be ... | 06/26/2001 |
| 6185252 | Process for decoding a digital signal and a bus system and a peripheral unit therefor In a method for decoding digital PWM signal and a bus system, a peripheral unit, and a device therefor, the digital signal is decoded by integrating the pulse width of each bit and then comparing the integration result with a reference signal. The bus sys... | 02/06/2001 |
| 6169423 | Method and circuit for regulating the length of an ATD pulse signal The invention relates to a method and a circuit for regulating a pulse synchronization signal (ATD) for the memory cell read phase in semiconductor integrated electronic memory devices. The pulse signal (ATD) is generated upon detection of a change in log... | 01/02/2001 |
| 6169765 | Apparatus and method for output signal pulse width error correction in a communications receiver An output signal pulse width error correction circuit and method wherein errors in a data signal conforming to a communications protocol having a prescribed duty cycle are corrected by monitoring a duty cycle of the data signal, comparing the duty cycle t... | 01/02/2001 |
| 6044037 | Semiconductor device A semiconductor device which enables quick and reliable adjustment of the address transition detection pulse width has an address transition detector (ATD) and n PMOS transistors connected in parallel to an output terminal, the PMOS transistors behaving a... | 03/28/2000 |
| 5936431 | Input signal variation detection circuit An input signal variation detection circuit effectively detects transitions of input signals from a memory apparatus. The circuit includes a plurality of unit blocks for detecting transitions of input signals and for outputting transition detection signal... | 08/10/1999 |
| 5912565 | Operation control circuit of power supply unit The disclosure is an operation control circuit of a power supply unit in a memory device which outputs a given operation control signal used for supplying a power supply voltage when a main control signal of the memory device is operating and additionally... | 06/15/1999 |
| 5874839 | Timer apparatus In a timer apparatus, the clock controlling circuit thereof outputs a clock signal during a period in which an input signal is significant. The counter thereof counts the number of pulses of the clock signal to generate a count-up signal when the value of... | 02/23/1999 |
| 5808484 | Method and apparatus for detecting changes in a clock signal to static states An integrated detection circuit (10) linearly charges capacitors (14) and (16) over time in response to particular states of an input signal (12). Outputs from the integrated detection circuit (10) are generated by differential pairs (39) when the charge ... | 09/15/1998 |
| 5734282 | Address transition detection circuit An improved address transition detection circuit prevents malfunctions of a memory by generating an address transition detection signal having a certain pulse width regardless of the width of a pulse of an address signal inputted to a memory. The circuit ... | 03/31/1998 |
| 5708375 | Minimum pulse width detector for a measurement instrument A detector circuit operating in parallel with a bandwidth limited measurement channel in a measurement instrument generates a warning signal when an input signal exceeds a predetermined repetition rate or has a pulse width less than a predetermined value.... | 01/13/1998 |
| 5646565 | Pulse-width-extension circuit and electronic device including the circuit A pulse-width-extension circuit for producing an output pulse signal whose pulse width is extended as compared with a pulse width of an input pulse signal when the pulse width of the input pulse signal is equal to or longer than a given width. The pulse-w... | 07/08/1997 |
| 5594379 | Method and Circuit to eliminate false triggering of power devices in optically coupled drive circuits caused by dv/dt sensitivity of optocouplers A circuit for eliminating false triggering of a power device in an optically coupled drive circuit caused by dv/dt sensitivity of an optocoupler of the drive circuit comprising a latch circuit having an input coupled to an output of the optocoupler and ha... | 01/14/1997 |
