Did You Know...
...that Robert Adler has the dubious distinction of being the Father of the Couch Potato? Back in 1955 Adler was employed by what was then Zenith Radio Corp., where he was charged to invent something that would allow viewers to turn down the TV volume without leaving their chairs. After a series of flops (such as a wired contraption that people tripped over), Adler hit on the idea of using sound waves. Thus the Remote Control was born...
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| Number | Title | Issue Date |
| 7466179 | Phase interpolation circuit The invention relates to a phase-interpolation circuit and a phase-interpolation signal generating circuit applying the phase-interpolation circuit. The phase-interpolation circuit can avoid short-circuit current effectively. In addition, an inter-phase signal can b... | 12/16/2008 |
| 7443217 | Circuit and method to balance delays through true and complement phases of differential and complementary drivers A circuit for balancing delays through true and complement phases of complementary drivers includes: a first driver; a second driver; a first delay device coupled to an input of the first driver and having an input coupled to an input signal node; a second delay dev... | 10/28/2008 |
| 7436234 | Signal oversampling for improved S:N in reflector movement system Eight or more transition points are generated during a given period, and are used in tracking movement of an interferometer reflector. Duty cycles of generated square waves are used to establish precise intervals between the transition points, and precise wave-phase... | 10/14/2008 |
| 7366966 | System and method for varying test signal durations and assert times for testing memory devices A testing system includes a phase interpolator receiving a clock signal. An output of the phase interpolator is coupled to both a first signal distribution tree that includes a first delay line in each of its branches and a second signal distribution tree that inclu... | 04/29/2008 |
| 7349510 | Apparatus for data recovery in a synchronous chip-to-chip system An apparatus that reduces sampling errors for data communicated between devices uses phase information acquired from a timing reference signal such as a strobe signal to align a data-sampling signal for sampling a data signal that was sent along with the timing refe... | 03/25/2008 |
| 7323913 | Multiphase divider for P-PLL based serial link receivers A multiphase divider includes a plurality of resetable dividers configured for performing resetable divider stages to a plurality of multiphase signals forming a plurality of divided multiphase signals having a monotonic increasing phase with equal spacing and an id... | 01/29/2008 |
| 7276949 | Multiphase clock generation A first-phase clock signal is generated in response to a first input clock signal. A second-phase clock signal is generated one clock cycle of the first input clock signal after generating the first-phase clock signal in response to the first input clock signal. A t... | 10/02/2007 |
| 7272742 | Method and apparatus for improving output skew for synchronous integrated circuits A method and apparatus for improving output skew across the data bus of a synchronous integrated circuit device. The device includes a clock input buffer that receives a system clock signal and generates a buffered clock signal, a delay line that receives the buffer... | 09/18/2007 |
| 7269094 | Memory system and method for strobing data, command and address signals A memory system couples command, address or write data signals from a memory controller to a memory device and read data signals from the memory device to the memory controller. A respective strobe generator circuit in each of the memory controller and the memory de... | 09/11/2007 |
| 7253673 | Multi-phase clock generator and generating method for network controller The present invention discloses a multi-phase clock generator of a network controller for generating a set of multi-phase clocks, and a method thereof. The multi-phase clock generator includes a first gating element and a second gating element. The first gating elem... | 08/07/2007 |
| 7253674 | Output clock phase-alignment circuit A clock generator has a reset circuit and (at least) two dividers, where each divider divides a reference clock signal by a divisor value to generate an output clock signal. The reset circuit generates reset signals for the dividers, where the reset signals are dela... | 08/07/2007 |
| 7251194 | Memory system and method for strobing data, command and address signals A memory system couples command, address or write data signals from a memory controller to a memory device and read data signals from the memory device to the memory controller. A respective strobe generator circuit in each of the memory controller and the memory de... | 07/31/2007 |
| 7245240 | Integrated circuit serializers with two-phase global master clocks Integrated circuit serializer circuitry is provided that converts parallel data to serial data on an integrated circuit. A two-phase global serializer master clock generator uses a four-phase internal clock to generate a two-phase global serializer master clock. The... | 07/17/2007 |
| 7245553 | Memory system and method for strobing data, command and address signals A memory system couples command, address or write data signals from a memory controller to a memory device and read data signals from the memory device to the memory controller. A respective strobe generator circuit in each of the memory controller and the memory de... | 07/17/2007 |
| 7203259 | Phase interpolator An arrangement for generating a clock signal. Embodiments provide a method, apparatus, system, and machine-readable medium to interpolate phases of a reference clock signal to output an interpolated clock signal. Some embodiments may output the clock signal as a rec... | 04/10/2007 |
| 7196564 | High frequency balanced phase interpolator A phase interpolation system includes an input stage that provides first and second modulated input signals having selected first and second relative phase angles. A weighting system is configured to steer a first portion of the first modulated input signal to an ou... | 03/27/2007 |
| 7187617 | Memory system and method for strobing data, command and address signals A memory system couples command, address or write data signals from a memory controller to a memory device and read data signals from the memory device to the memory controller. A respective strobe generator circuit in each of the memory controller and the memory de... | 03/06/2007 |
| 7142033 | Differential clocking scheme in an integrated circuit having digital multiplexers A system for distributing a small signal differential signal to a circuit element. The system includes: a first converter configured to convert a first small signal differential signal to a first two phase full CMOS differential signal for input into the differentia... | 11/28/2006 |
| 7126874 | Memory system and method for strobing data, command and address signals A memory system couples command, address or write data signals from a memory controller to a memory device and read data signals from the memory device to the memory controller. A respective strobe generator circuit in each of the memory controller and the memory de... | 10/24/2006 |
| 7126406 | Programmable logic device having an embedded differential clock tree A clock distribution network having: a backbone clock signal line configured to provide a differential clock signal; multiple branches coupled to the backbone clock signal line for distributing the differential clock signal to multiple programmable function elements... | 10/24/2006 |
| 7119602 | Low-skew single-ended to differential converter A single-ended to differential converter uses a cross-coupled latch that maximizes the output zero-crossing symmetry and is self compensating over PVT variations. An in-phase driving signal is provided by an always-on transmission gate coupled to the input. An out-o... | 10/10/2006 |
| 7102404 | Interpolator circuit An improved interpolator includes a replica delay line and an interpolated delay edge generator. The replica delay line provides two replica delay edges to the interpolated delay edge generator. The interpolated delay edge generator selectively generates an interpol... | 09/05/2006 |
| 7098707 | Highly configurable PLL architecture for programmable logic A programmable logic device includes configurable phase-locked loop (PLL) circuitry that outputs multiple clock signals having programmable phases and frequencies. Each output signal is programmably selectable for use as an external clock, internal global clock, int... | 08/29/2006 |
| 7085993 | System and method for correcting timing signals in integrated circuits A system and method for dynamically altering a clock speed of a clock signal used for timing of data signal transmissions and receptions within an integrated circuit (IC) device. The system includes a clock generator circuit for providing a clock signal used for tim... | 08/01/2006 |
| 7078949 | Analog delay locked loop having duty cycle correction circuit An analog delay locked loop device includes a first block for receiving an internal clock signal and a reference clock signal to generate normal multi phase clock signal pairs and dummy multi phase clock signal pairs; and a second block for receiving the reference c... | 07/18/2006 |
| 7071756 | Clock multiplexing system A clock control circuit in an integrated circuit for providing a differential clock signal to a differential clock tree. The clock control circuit includes: first differential multiplexers configured to select first outputs from the input clock signals; second diffe... | 07/04/2006 |
| 7043392 | Interpolator testing system According to some embodiments, a device includes an interpolator to receive at least a first clock signal having a first clock phase and to receive a second clock signal having a second clock phase. The interpolator may include a first plurality of interpolator legs... | 05/09/2006 |
| 7034596 | Adaptive input logic for phase adjustments Systems and methods are disclosed to provide static and/or dynamic phase adjustments to a data signal relative to a clock signal. For example, the data signal may be delayed by a coarse delay and/or a fine delay to match the timing of the clock signal independently ... | 04/25/2006 |
| 7030674 | Multiphase clock generators Multiphase clock generators and methods are provided. A multiphase clock generator has a first clock divider for generating a first-phase clock signal from a first input clock signal. A first logic gate is connected to an output port of the first clock divider. A se... | 04/18/2006 |
| 7030673 | Phase splitter circuit A phase splitter circuit includes a first signal generator and a second signal generator. The first signal generator generates a first signal in response to an input signal. The second signal generator generates a second signal in response to the input signal. The p... | 04/18/2006 |
| 7009441 | Phase multiplier circuit So as to generate multiple output signals whose phases are evenly spaced about 360 degrees, and having a frequency equal to that of an input signal, a phase multiplier circuit includes three or more instances of a phase multiplier subcircuit and additional circuitry... | 03/07/2006 |
| 6998885 | Apparatus and method for delay matching of full and divided clock signals A transition delay matching circuit in which the transition delay of the divided clock signal is substantially the same as the transition delay of the reference clock signal. The transition delay of the divided clock signal is adjusted by reducing the steady state a... | 02/14/2006 |
| 6995595 | Direct conversion receiver having a DC offset eliminating function A direct conversion receiver having a DC offset eliminating function that eliminates a DC offset component in which an oscillator generates a local frequency signal, A first phase shifter shifts a phase of the local frequency signal from the oscillator by 90°, a fi... | 02/07/2006 |
| 6980480 | Multi-frequency synchronizing clock signal generator An apparatus and method for generating a plurality of synchronizing signals for synchronizing operation of the device in which the apparatus is located, such as in semiconductor memory devices. The apparatus can generate a plurality of synchronizing signals based on... | 12/27/2005 |
| 6956423 | Interleaved clock signal generator having serial delay and ring counter architecture The interleaved clock generator generates N interleaved clock signals in response to an input clock signal. The interleaved clock generator comprises an interleaved clock generator of a first type for receiving the input clock signal and for generating M interleaved... | 10/18/2005 |
| 6946870 | Control of simultaneous switch noise from multiple outputs Output switch noise resulting from simultaneous switching is reduced by time multiplexing the output switching operation. A plurality of phase-shifted clock signals are generated such that each of the phase-shifted clock signals exhibits an active (e.g., rising) edg... | 09/20/2005 |
| 6940328 | Methods and apparatus for duty cycle control An electronic system according to various aspects of the present invention comprises a signal generator configured to generate a first signal and a duty cycle correction circuit configured to be responsive to the first signal and provide a corrected signal having a ... | 09/06/2005 |
| 6919750 | Clock signal generation circuit used for sample hold circuit A master DLL circuit (3) generates a first delay signal (CKD) by delaying the master clock signal by a first delay time (T0) and generates a first pulse signal (Smp) having a pulse width (T0) of the first delay time, and generates a first contro... | 07/19/2005 |
| 6914852 | Multi-frequency synchronizing clock signal generator An apparatus and method for generating a plurality of synchronizing signals for synchronizing operation of the device in which the apparatus is located, such as in semiconductor memory devices. The apparatus can generate a plurality of synchronizing signals based on... | 07/05/2005 |
| 6906564 | Apparatus and method for delay matching of full and divided clock signals A transition delay matching circuit in which the transition delay of the divided clock signal is substantially the same as the transition delay of the reference clock signal. The transition delay of the divided clock signal is adjusted by reducing the steady state a... | 06/14/2005 |
