Microwave Oven With Removable Storage Cassette in Dashboard of Motor Vehicle
A microwave oven adapted for use within a motor vehicle dashboard area. The microwave oven has a removable storage cassette, and slidable platforms for securing and serving containers of beverages and foods.
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| Number | Title | Issue Date |
| 7333579 | Robust symbol timing recovery circuit for telephone line modem A robust symbol timing recovery circuit for a telephone line modem is provided. The symbol timing recovery circuit comprises a timing estimator and an interpolator. The timing estimator, which performs an operation on input samples and estimates a timing offset of a... | 02/19/2008 |
| 7327174 | Fast locking mechanism for delay lock loops and phase lock loops A fast lock mechanism for delay lock loops and phase lock loops. A first circuit is coupled to receive an input clock signal and to generate an output clock signal responsive to the input clock signal. The first circuit includes a charge pump and delay cells. The ch... | 02/05/2008 |
| 7302011 | Quadrature frequency doubling system The frequency doubler of the present invention operates to provide an in-phase signal and a quadrature signal, each having a frequency equal to twice the frequency of a reference signal. The in-phase and quadrature signals are based on signals that are 0 degrees, 45... | 11/27/2007 |
| 7203259 | Phase interpolator An arrangement for generating a clock signal. Embodiments provide a method, apparatus, system, and machine-readable medium to interpolate phases of a reference clock signal to output an interpolated clock signal. Some embodiments may output the clock signal as a rec... | 04/10/2007 |
| 7197101 | Phase interpolator based clock recovering An arrangement for a phase interpolator based clock recovery system, a phase interpolator, and a voltage controller for a highly linear phase interpolator system is provided. Embodiments comprise a method, apparatus, system, and machine-readable medium to recover a ... | 03/27/2007 |
| 7196562 | Programmable clock drivers that support CRC error checking of configuration data during program restore operations A packaged integrated circuit device includes a nonvolatile memory device and a programmable clock driver circuit therein. The memory device may be provided as an EEPROM device that is disposed on a first integrated circuit substrate and the programmable clock drive... | 03/27/2007 |
| 7196564 | High frequency balanced phase interpolator A phase interpolation system includes an input stage that provides first and second modulated input signals having selected first and second relative phase angles. A weighting system is configured to steer a first portion of the first modulated input signal to an ou... | 03/27/2007 |
| 7187917 | Current interpolation in multi-phase local oscillator for use with harmonic rejection mixer A circuit provides a reduced harmonic content output signal OUTA and/or OUTB that is modulated according to an input signal 231. The circuit has an oscillator circuit 210 and a harmonic rejection mixer (HRM) 230. The oscillator circuit 210 | 03/06/2007 |
| 7151398 | Clock signal generators having programmable full-period clock skew control Clock signal generators include an integrated circuit chip having a PLL-based or DLL-based clock driver therein. The clock driver is configured to support generation of a plurality of clock signals having different frequencies in a range between 1 and 1/N times a fr... | 12/19/2006 |
| 7151813 | Techniques to reduce transmitted jitter A re-timer system that may include a phase recoverer (“PR”), first-in-first-out device (“FIFO”) and retime clock multiplication unit (“CMU”). PR may receive an input signal that suffers from jitter. PR may generate a phase matched signal having substanti... | 12/19/2006 |
| 7099373 | Noise shaping technique for spread spectrum communications A spread spectrum noise shaper uses a modulation technique to achieve a greater signal-to-noise or signal-to-interference ratio (SNR or SIR). The technique doubles the system SIR, in principle. This doubling yields a doubling in system capacity. SNR is increased by ... | 08/29/2006 |
| 7088191 | Delay interpolation in a ring oscillator delay stage According to some embodiments, a circuit includes a delay stage of a ring oscillator. The delay stage may include a first differential pair, a second differential pair, and a third differential pair. The first differential pair may be coupled to a first current-stee... | 08/08/2006 |
| 7053687 | Binary hysteresis comparator circuits and methods Binary hysteresis comparator circuits, methods, and applications. A binary constant defines a window within which a binary input can change its value without triggering the comparator circuit output signal. An exemplary binary hysteresis comparator circuit includes ... | 05/30/2006 |
| 6999678 | Adaptive method for chirping an optical data signal An adaptive method is provided for applying chirp to an optical signal traversing through an optical network. The adaptive method comprises: applying chirp to an optical data signal at a transmitter in the optical network; transmitting the optical data signal throug... | 02/14/2006 |
| 6995593 | Circuit for programmable stepless clock shifting The present invention provides for a circuit for programmable stepless clock shifting, consisting of a splitter generating a 0° and a 90° shifted clocks from a reference clock, and an interpolator of the two shifted clocks, which provides at the output the desired... | 02/07/2006 |
| 6995594 | Phase interpolator device and method A high-speed serial data transceiver includes multiple receivers and transmitters for receiving and transmitting multiple analog, serial data signals at multi-gigabit-per-second data rates. Each receiver includes a timing recovery system for tracking a phase and a f... | 02/07/2006 |
| 6977539 | Clock signal generators having programmable full-period clock skew control and methods of generating clock signals having programmable skews Clock signal generators include an integrated circuit chip having a PLL-based or DLL-based clock driver therein. The clock driver is configured to support generation of a plurality of clock signals having different frequencies in a range between 1 and 1/N times a fr... | 12/20/2005 |
| 6931089 | Phase-locked loop with analog phase rotator A phase-locked loop includes a phase detector which receives an input signal and a first internal periodic signal and provides a phase signal indicative of a phase difference between the input signal and the internal signal. A rotator then receives the phase signal ... | 08/16/2005 |
| 6922451 | Frequency shifting circuit and method This invention is regarding a frequency shifting circuit suitable for a digital demodulator in a multi-carrier communications system. After converting analog signal vectors to the input signal vectors according to a predetermined sampling clock, control data is gene... | 07/26/2005 |
| 6815993 | π/2 phase shifter In a π/2 phase shifter, first and second signals and first and second inverted signals are produced based on input signals. The first and second signals have the same amplitude and are out of phase from each other, and the first and second inverted signals respecti... | 11/09/2004 |
| 6791388 | Phase interpolator device and method A high-speed serial data transceiver includes multiple receivers and transmitters for receiving and transmitting multiple analog, serial data signals at multi-gigabit-per-second data rates. Each receiver includes a timing recovery system for tracking a phase and a f... | 09/14/2004 |
| 6777993 | Method and apparatus for adjusting the phase and frequency of a periodic wave A delay circuit includes a phase vernier having a plurality of logic components. Each logic component includes a selectable injection input capable of adjusting a phase of an input to the phase vernier. ... | 08/17/2004 |
| 6677796 | Method and apparatus for implementing precision time delays A system and method of implementing precision time delays that provides important and novel improvements over prior techniques of implementing time delays by utilizing a new strategy for selecting the values in the sine and cosine lookup tables. Sine and ... | 01/13/2004 |
| 6617893 | Digital variable clock divider A clock divider circuit and methods of operating same includes a standard integral clock divider circuit and a phase slip non-integral divider circuit for high granularity non-integral clock division. A multi-phase frequency synthesizer produces a plurali... | 09/09/2003 |
| 6525580 | Circuit and method for multi-phase alignment A method and circuit for adjusting clock pulse widths in a high speed sample and hold circuit. A single phase clock signal is input into a pulse discriminator and separated into rising and falling edges. The edges are adjusted to a desired slope. The adju... | 02/25/2003 |
| 6509773 | Phase interpolator device and method A high-speed serial data transceiver includes multiple receivers and transmitters for receiving and transmitting multiple analog, serial data signals at multi-gigabit-per-second data rates. Each receiver includes a timing recovery system for tracking a ph... | 01/21/2003 |
| 6437620 | Circuit and method for multi-phase alignment A method and circuit for adjusting clock pulse widths in a high speed sample and hold circuit. A single phase clock signal is input into a pulse discriminator and separated into rising and falling edges. The edges are adjusted to a desired slope. The adju... | 08/20/2002 |
| 6417712 | Phase shifter using sine and cosine weighting functions Sine and cosine weighting functions are applied to phase quadrature versions of an input signal to be phase shifted, and the weighted results are summed to provide a phase shifted output signal with an amplitude which is relatively independent of the phas... | 07/09/2002 |
| 6404255 | Phase shift apparatus A source (20) provides an input signal (S1) to be phase shifted and a combining circuit (24) concurrently combines first (A), second (B) and third (C) intermediate signals derived from the input signal (S1), and having differing phase shifts (0, -45, +135... | 06/11/2002 |
| 6340908 | Phase adjusting circuit, scaling signal generation circuit using phase adjusting circuit, and position measuring apparatus using scaling signal generation circuit A phase adjusting circuit including an input level adjuster using two detection signals having different phases and adjusting an amplitude of at least one detection signal to a predetermined level and a signal processor for signal processing including at ... | 01/22/2002 |
| 6310502 | Broadband phase shifting circuit having two phase shifter branches connected in parallel A broadband phase-shifting circuit, in particular for an IQ modulator, has two phase-shifting branches connected in parallel, to the input of which is supplied the input signal of which the phase is to be shifted, and which supply at their outputs output ... | 10/30/2001 |
| 6208183 | Gated delay-locked loop for clock generation applications A gated-delay locked loop that generates an output clock in phase with and having a frequency which is an integer multiple of the frequency of a reference clock. The gated delay-locked loop includes a voltage-controlled gated oscillator having first and s... | 03/27/2001 |
| 6051996 | Phase detector The present invention is a method and an apparatus for measuring phase differences between signals A and B using an absolute voltage value for each phase difference between b1;180°. This is accomplished using a third signal C, which is a signal having ... | 04/18/2000 |
| 6025750 | Digital filter with long impulse response A digital filter includes a)--a plurality of means for the sampling (10, 11, 12, 13, 20, 21, 22, 30, 31) with different delays, of an incoming signal (S), and b)--means (7) to carry out a linear combination of samples produced by the said sampling means (... | 02/15/2000 |
| 5808497 | Digital phase shifter The present invention provides a method of and an apparatus for producing an output signal which is, relative to a periodic input signal, delayed by a predetermined phase angle phi. Initially, the phase angle phi between 0 and 2π is divided by 2π and mu... | 09/15/1998 |
| 5767705 | Frequency converting circuit A frequency converting circuit has a phase divider, a switching circuit, and switching pulse generator. The phase divider divides a phase of a first input signal and outputting m-units of channel signals having a same frequency but different phases shifte... | 06/16/1998 |
| 5485128 | Oscillation circuit having a current-controlled phase shift circuit An oscillator circuit including a current-controlled phase shift circuit and a feedback circuit including a quartz resonator is capable of varying the oscillation frequency in accordance with control current signals. A phase shift circuit included in the ... | 01/16/1996 |
| 5485108 | Delayed detection type demodulator Within the differential detection demodulator, the received signal is first quantized by a limiter amplifier 10 and then subjected to frequency conversion by a frequency converter 50 including: an exclusive OR element 51; a running average generator 52 co... | 01/16/1996 |
| 4935701 | Phase shift circuit A phase shift circuit used in a regenerating repeater, includes a separating unit for separating an input signal into two separate signals having a phase difference of a phase angle of 90° therebetween, one separated signal having a "0" phase and the oth... | 06/19/1990 |
| 4924188 | Spread spectrum receiver having phase shifter for effecting phase synchronization of two convolvers A phase shifter is disclosed which performs a desired phase shift by distributing an input signal to two signals whose phases are different by 90° from each other which signals are added to each other after having been weighted with a sine and a cosine f... | 05/08/1990 |