Class 327/247 - Having multiple outputs

Subclass of Class 327 - Miscellaneous active electrical nonlinear devices, circuits, and systems
Definition: Subject matter wherein more than one output is produced.
No. of patents: 40
Last issue date: 05/06/2008

Number	Title	Issue Date
7368974	Signal adder circuit capable of removing effects due to phase error or amplitude error of I and Q signals A signal adder circuit includes: an adding unit that includes at least a pair of amplification elements in which a constant current flows between ground terminals and a ground, input signals having different phases are input to input terminals, and output terminals ...	05/06/2008
7366966	System and method for varying test signal durations and assert times for testing memory devices A testing system includes a phase interpolator receiving a clock signal. An output of the phase interpolator is coupled to both a first signal distribution tree that includes a first delay line in each of its branches and a second signal distribution tree that inclu...	04/29/2008
7332950	DLL measure initialization circuit for high frequency operation A memory device, delay lock loop circuit (DLL) and DLL reset circuitry are described. The DLL includes a shift register and a measured delay for pre-loading the shift register. The reset circuitry selectively filters a clock signal propagation through the measured d...	02/19/2008
7298195	Methods and apparatus for improved phase switching and linearity in an analog phase interpolator Methods and apparatus are provided for improving phase switching and linearity in an analog phase interpolator. A phase interpolator in accordance with the present invention comprises (i) a plurality of tail current sources that are activated for substantially all t...	11/20/2007
7282979	Phase shifting device A phase shifting device includes a signal source; a variable phase shifter; first and second doubling circuits; and a 90-degree phase comparator. An output from the signal source is connected to an input of the variable phase shifter and to an input of the second do...	10/16/2007
7205811	Methods and apparatus for maintaining desired slope of clock edges in a phase interpolator using an adjustable bias Methods and apparatus are provided for maintaining a desired slope of clock edges in a phase interpolator using an adjustable bias. The disclosed phase interpolator comprises at least one delay element to generate at least two interpolation signals each having an as...	04/17/2007
7196562	Programmable clock drivers that support CRC error checking of configuration data during program restore operations A packaged integrated circuit device includes a nonvolatile memory device and a programmable clock driver circuit therein. The memory device may be provided as an EEPROM device that is disposed on a first integrated circuit substrate and the programmable clock drive...	03/27/2007
7196564	High frequency balanced phase interpolator A phase interpolation system includes an input stage that provides first and second modulated input signals having selected first and second relative phase angles. A weighting system is configured to steer a first portion of the first modulated input signal to an ou...	03/27/2007
7173466	Timing signal generating circuit having simple configuration with low supply voltage and generating timing signals with high accuracy A timing signal generating circuit receives multiphase input signals and generates a signal having a phase intermediate therebetween, and weighting is applied to the multi-phase input signals by using a variable impedance circuit. The timing signal generating circui...	02/06/2007
7151398	Clock signal generators having programmable full-period clock skew control Clock signal generators include an integrated circuit chip having a PLL-based or DLL-based clock driver therein. The clock driver is configured to support generation of a plurality of clock signals having different frequencies in a range between 1 and 1/N times a fr...	12/19/2006
7142029	Operational frequency range of latch circuits Described herein is a latch circuit (110) which has an improved maximum toggle rate or frequency. The latch circuit (110) includes a first portion (116) and a second portion (62) in which input clock signals (52,54) are applied to ...	11/28/2006
7135905	High speed clock and data recovery system A clock and data recovery system for detecting and resolving meta-stability conditions is provided. The clock and data recovery system includes a phase detector having logic configured to detect a meta-stability condition and to generate an output signal to mitigate...	11/14/2006
7123070	High frequency gain amplifier with phase compensation circuit A gain amplifier with quadrature phase compensation circuit is disclosed. The gain amplifier for in-phase (“I”) and quadrature (“Q”) signals comprises a first resistive component having a first input node (“Node 1”) and a first output node (“Nod...	10/17/2006
7119617	Differential amplifier A differential amplifier suitably adapted to an ultra-high-speed signal transmitting apparatus. The differential amplifier includes a first inductor located between a differential transistor and a gate grounded transistor, an optional second inductor located between...	10/10/2006
7106117	Delayed clock signal generator A device which may be configured to generate delayed clock signals by a specified phase difference, which may include a clock generator circuit for generating at least one clock signal, a delayed clock signal generator for delaying the at least one clock signal, a p...	09/12/2006
7093041	Dual purpose PCI-X DDR configurable terminator/driver A dual purpose PCI-X DDR configurable terminator/driver providing programmable termination of the interface in a PCI-X system a plurality of N-channel devices divided into at least two groups and a plurality of P-channel devices also divided into at least two groups...	08/15/2006
6999547	Delay-lock-loop with improved accuracy and range A Delay-Lock-Loop circuit and a method for producing a phase shift comprises a phase generator producing a first and second clock signal having a first and second rising edge, respectively, wherein a timing difference between the first and second rising edges is equ...	02/14/2006
6977539	Clock signal generators having programmable full-period clock skew control and methods of generating clock signals having programmable skews Clock signal generators include an integrated circuit chip having a PLL-based or DLL-based clock driver therein. The clock driver is configured to support generation of a plurality of clock signals having different frequencies in a range between 1 and 1/N times a fr...	12/20/2005
6960948	System with phase jumping locked loop circuit An integrated circuit device having a select circuit, a summing circuit and a phase mixer. The select circuit selects one of a plurality of offset values as a selected offset. The summing circuit sums the selected offset with a phase count value, the phase count val...	11/01/2005
6956407	Pre-emphasis circuitry and methods Pre-emphasis is given to differential output signals emanating from a pair of output nodes by initially (after an input data signal transition) connecting at least two current circuits to only one of the nodes. After a time delay, one of the current circuits is swit...	10/18/2005
6952123	System with dual rail regulated locked loop An integrated circuit device having a select circuit, a summing circuit and a phase mixer. The select circuit selects one of a plurality of offset values as a selected offset. The summing circuit sums the selected offset with a phase count value, the phase count val...	10/04/2005
6943606	Phase interpolator to interpolate between a plurality of clock phases A phase interpolator interpolates between a plurality of clock phases using a plurality of switching legs coupled to a common output. Each switching leg includes a pair of differential switching transistors each having a gate and two additional terminals, one of whi...	09/13/2005
6922091	Locked loop circuit with clock hold function A locked loop circuit having a clock hold function. The locked loop circuit includes a select circuit, phase mixing circuit, hold signal generator and latch circuit. The select circuit selects one of a plurality of phase values in response to a select signal, and th...	07/26/2005
6919749	Apparatus and method for a digital delay locked loop A circuit and method is shown for digital control of delay lines in a delay locked loop (DLL) system. A pair of multiplexors (MUXes) is used to select output taps from a pair of complementary delay lines that delay a reference clock signal in order to lock onto a re...	07/19/2005
6911853	Locked loop with dual rail regulation An apparatus having a dual rail regulated reference loop. The reference loop includes a delay circuit powered by upper and lower supply voltages to generate a plurality of reference clock signals, and a voltage regulation circuit to adjust the upper and lower supply...	06/28/2005
6911857	Current controlled delay circuit A current controlled delay circuit is disclosed. Two currents of constant sum are generated to control the delay of the circuit. The circuit includes a differential pair to switch one of the two currents from one leg of the circuit to another leg of the circuit. The...	06/28/2005
6853230	Method and apparatus for producing a clock output signal An apparatus for producing a clock output signal, having an input for receiving an input signal containing a phase information item; a clock generator for producing a multiplicity of clock signals whose phases are respectively shifted from one another by a predeterm...	02/08/2005
6815993	π/2 phase shifter In a π/2 phase shifter, first and second signals and first and second inverted signals are produced based on input signals. The first and second signals have the same amplitude and are out of phase from each other, and the first and second inverted signals respecti...	11/09/2004
RE38499	Two-stage amplifier for active pixel sensor cell array for reducing fixed pattern noise in the array output An active pixel sensor cell array in which a two-stage amplifier amplifies the output of each cell. The two-stage amplifier design reduces fixed pattern noise in the image data generated by reading the array, by providing increased gain for the output of each cell w...	04/20/2004
6531924	Bias method and circuit for distortion reduction The present invention provides a technique for selective cancellation of the 2nd -order or 3rd -order nonlinearity of a transistor. Any nonlinearity is a function of the bias voltage of a transistor. In many cases, this function is s...	03/11/2003
6384653	Linearly controlled CMOS phase interpolator Method and system for providing a signal with a controllable zero crossing time value. The system provides first and second two-sided triangular wave signals, identical but shifted by a selected fraction f.multidot.T of a period T of either triangular sig...	05/07/2002
6246721	Termination structure based on the cancellation of the reflected wave A termination structure is shown whereby multiple transmission lines designed to have the same intrinsic impedance and same delay are driven from a central node. The central node is driven by a driver and calibration resistor connected in series to produc...	06/12/2001
6133773	Variable delay element A method and apparatus for an adjustable phase interpolator is provided. The adjustable phase interpolator includes a phase interpolator circuit that has a voltage input and a voltage output. The adjustable phase interpolator further includes a controllab...	10/17/2000
5939918	Electronic phase shifter An electronic phase shifter splits an input signal into two signals whose amplitudes are set by a weighting circuit controlled by a phase shift control signal. Each of the two outputs of the weighting circuit is loaded with an RLC resonator, one tuned to ...	08/17/1999
5635863	Programmable phase comparator A programmable phase comparator comprises a switch circuit operable in response to first and second signals to provide an output signal representative of the phase relationship of the first and second signals. A reference signal is applied to the switch c...	06/03/1997
4922127	Phase shift arrangement A phase shift arrangement comprising bi-stable devices arranged to provide phase shifted output signals triggered by a clock pulse level. The bi-stable devices including biasing means such that the clock pulse level at which the bi-stable devices are trig...	05/01/1990
4795922	Amplitude and phase discriminator using all-pass networks An amplitude/phase discriminator network the entirety of which is integrated on the same (GaAs) semiconductor chip, obtains a quadrature phase split through the use of a pair of orthogonal phase generators each of which comprises an all-pass network coupl...	01/03/1989
4647791	Generator for producing multiple signals which are synchronous with each other A voltage comparator with several parallel output channels connected to respective threshold circuits is responsive to the increase of the charge voltage of a capacitor with a linear variation of output currents in the channels. The different output curre...	03/03/1987
4435656	Phase inverter circuit A phase-inverter circuit comprising two differential current gates each comprising three transistors, the emitters of which are separated from ground by a gate current source. The signal to be inverted is applied across the bases of first and second trans...	03/06/1984
4270061	Current transformer input system for AC conversion devices An improved input system for isolating resolver or synchro outputs from inputs to demodulators or analog-to-digital converters uses current transformers rather than voltage transformers. The resistances of resistors connected in series with the primary wi...	05/26/1981

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Class 327/247 - Having multiple outputs