"It is my heart-warmed and world-embracing Christmas hope and aspiration that all of us, the high, the low, the rich, the poor, the admired, the despised, the loved, the hated, the civilized, the savage (every man and brother of us all throughout the whole earth), may eventually be gathered together in a heaven of everlasting rest and peace and bliss, except the inventor of the telephone. "
Mark Twain ; Christmas greetings, 1890
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| Number | Title | Issue Date |
| 7808291 | Jitter generating circuit A jitter generating circuit wherein a simple structure can be used to generate a pattern effect jitter. A jitter generating circuit 1 comprises a driver input circuit 20 that serves as a signal analyzing unit for analyzing the contents of the signal pa... | 10/05/2010 |
| 7498858 | Interpolator systems with linearity adjustments and related methods Embodiments of an interpolator system and method are disclosed. One embodiment of an interpolator system, among others, includes an interpolator having first and second output terminals providing output signals; a comparator coupled to the first and second output te... | 03/03/2009 |
| 7408994 | AC coupling system for wide band digital data with dynamic AC load An interface system couples a fixed impedance device to a receiver for transmitting data signals at different data rates at different times. The interface system includes elements that are connected to provide different time constants of responsiveness to data signa... | 08/05/2008 |
| 7366966 | System and method for varying test signal durations and assert times for testing memory devices A testing system includes a phase interpolator receiving a clock signal. An output of the phase interpolator is coupled to both a first signal distribution tree that includes a first delay line in each of its branches and a second signal distribution tree that inclu... | 04/29/2008 |
| 7301383 | Circuit for controlling phase with improved linearity of phase change A circuit for controlling phase includes a first node providing a current responsive to a first clock signal, a first plurality of switch circuits coupled to the first node, a first plurality of current supply sources coupled to the first plurality of switch circuit... | 11/27/2007 |
| 7283596 | PAM-4 data slicer having symmetrical offset A PAM-4 data slicer includes first, second, and third comparators which provide first, second, and third thresholds, respectively. Each of the comparators has an offset. The first and third comparators have an offset generating arrangement at their outputs to provid... | 10/16/2007 |
| 7274276 | Amplifier circuit, gyrator circuit, filter device and method for amplifying a signal An amplifier circuit comprising a transconductor device connected to a phase shifter section. The phase shifter section has an adjustable phase shift and an impedance at least partially dependent of the frequency of an input signal. In use, the adjustable phase shif... | 09/25/2007 |
| 7259521 | Video driver architecture for AMOLED displays An AMOLED display system, including an AMOLED display panel receiving a video signal, includes a video driver receiving the video signal and generating a video drive signal indicative of the video signal and referenced to a positive power supply voltage of the displ... | 08/21/2007 |
| 7196564 | High frequency balanced phase interpolator A phase interpolation system includes an input stage that provides first and second modulated input signals having selected first and second relative phase angles. A weighting system is configured to steer a first portion of the first modulated input signal to an ou... | 03/27/2007 |
| 7187243 | Delay circuit A delay circuit according to embodiments of the present invention capable of operating over a wide range of frequencies is presented. Embodiments of the invention minimize or eliminate parasitic capacitance at the output terminals that arise from switching elements ... | 03/06/2007 |
| 7180352 | Clock recovery using clock phase interpolator A clock recovery circuit includes a delay locked loop, and a clock phase interpolator circuit. The delay locked loop provides multiple phases of an input clock signal to the interpolator circuit, which interpolates between two of the clock phases to provide a clock ... | 02/20/2007 |
| 7126431 | Differential delay cell having controllable amplitude output A differential delay cell includes a current source for establishing an operating current and a differentially coupled transistor pair having a common node, two input nodes, and two output nodes. The common node is coupled to the current source, and the two output n... | 10/24/2006 |
| 7043392 | Interpolator testing system According to some embodiments, a device includes an interpolator to receive at least a first clock signal having a first clock phase and to receive a second clock signal having a second clock phase. The interpolator may include a first plurality of interpolator legs... | 05/09/2006 |
| 6999745 | Mixer with a variable gain current-to-voltage converter A receiver comprising an input for receiving a first signal, said receiver further comprising a local oscillator for generating a periodical signal. The receiver further comprises a mixer for generating a third signal representative for a combination of a second sig... | 02/14/2006 |
| 6952378 | Method for on-die detection of the system operation frequency in a DRAM to adjust DRAM operations The present invention relates to a method of operating a memory system comprising a memory chip. An operating signal is generated at an operating frequency. The operating frequency is applied to the memory chip to control one or more electrical components of the mem... | 10/04/2005 |
| 6943606 | Phase interpolator to interpolate between a plurality of clock phases A phase interpolator interpolates between a plurality of clock phases using a plurality of switching legs coupled to a common output. Each switching leg includes a pair of differential switching transistors each having a gate and two additional terminals, one of whi... | 09/13/2005 |
| 6903591 | Phase shifter circuit A phase shift circuit that generates a phase shift signal whose amplitude matches at a plurality of frequencies without increasing the circuit area. The phase shifter circuit includes first and second differential amplifiers which generate first and second first pha... | 06/07/2005 |
| 6744296 | Circuits and methods for accurately setting a phase shift Circuits and methods for providing an accurate phase shift between a generated output signal and an input signal are disclosed. The circuits and methods enable any amount of accurate phase shift to be set without requiring significant changes in circuitry with each ... | 06/01/2004 |
| 6583658 | Balanced circuit arrangement The invention relates to a balanced circuit arrangement for converting an asymmetric analogous input signal (S1) into a symmetrical output signal (S2, S3). A first amplifier (2) is provided, whereby the non-inverting input thereof is connected to the anal... | 06/24/2003 |
| 6452434 | Phase shifter circuit A phase shift circuit that generates a phase shift signal whose amplitude matches at a plurality of frequencies without increasing the circuit area. The phase shifter circuit includes first and second differential amplifiers which generate first and secon... | 09/17/2002 |
| 6359486 | Modified phase interpolator and method to use same in high-speed, low power applications A phase interpolator that receives input clock phase and selection inputs that are distinct from the input clock phases. The phase interpolator generates an output clock phase based on the selection inputs. The phase interpolator includes selector devices... | 03/19/2002 |
| 6340909 | Method and apparatus for phase interpolation A phase interpolater circuit includes a first adjustable current supply to generate a first current that is based on the amplitude of a first controlled voltage and a first current mirror circuit to generate a second current that is based on the first cur... | 01/22/2002 |
| 6340908 | Phase adjusting circuit, scaling signal generation circuit using phase adjusting circuit, and position measuring apparatus using scaling signal generation circuit A phase adjusting circuit including an input level adjuster using two detection signals having different phases and adjusting an amplitude of at least one detection signal to a predetermined level and a signal processor for signal processing including at ... | 01/22/2002 |
| 6285228 | Integrated circuit for generating a phase-shifted output clock signal from a clock signal The integrated circuit generates an output clock signal with a phase shift relative to a first clock signal. The currents IE =I1 and IL =I2 can be weighted differently by means of control signals. A different ph... | 09/04/2001 |
| 6255877 | Wide range, variable phase shift circuit A filter includes an FET and a capacitor in a phase shift network wherein the FET operates as a variable resistor. An impedance multiplier is coupled to the FET for increasing the range of resistance of the FET.... | 07/03/2001 |
| 6225864 | RF amplifier having a dual slope phase modulator An RF amplifier system and method are presented herein for varying the phase of an RF signal made up of a first train of pulses exhibiting a fixed frequency and fixed duty pulse cycle and wherein each pulse is of a fixed amplitude and duration. An integra... | 05/01/2001 |
| 6194933 | Input circuit for decreased phase lag An input circuit for use in a semiconductor integrated circuit decreases a phase lag between a clock signal and an input signal. The input circuit includes a first amplifier that receives an external clock signal at a first input and a reference voltage s... | 02/27/2001 |
| 6133773 | Variable delay element A method and apparatus for an adjustable phase interpolator is provided. The adjustable phase interpolator includes a phase interpolator circuit that has a voltage input and a voltage output. The adjustable phase interpolator further includes a controllab... | 10/17/2000 |
| 6121809 | Accurate and tuneable active differential phase splitters in RFIC wireless applications A differential phase splitter circuit for producing opposite phase signals from an input AC signal is provided. A first and second transistor is provided. The source of these transistors are connected to a common first node. Further, these transistors act... | 09/19/2000 |
| 5945860 | CLM/ECL clock phase shifter with CMOS digital control A CML/ECL clock phase shifter device provides a 360° phase control range and, upon being provided with two CML clock signals related by a known phase difference, the device produces any desired phase in response to a control signal. The device uses a CMO... | 08/31/1999 |
| 5945863 | Analog delay circuit An analog delay circuit provide a current-dependent delay through two differential pairs of transistors operated in parallel, one with input resistors, the other without. Delay is varied through the delay stage by provision of complementary currents produ... | 08/31/1999 |
| 5939917 | Voltage-controlled phase shifter The present invention relates to a voltage-controlled phase shifter including two differential stages, each including a biasing branch and output branches coupled with the output branches of the other stage; two first resistors coupling the output branche... | 08/17/1999 |
| 5939918 | Electronic phase shifter An electronic phase shifter splits an input signal into two signals whose amplitudes are set by a weighting circuit controlled by a phase shift control signal. Each of the two outputs of the weighting circuit is loaded with an RLC resonator, one tuned to ... | 08/17/1999 |
| 5896053 | Single ended to differential converter and 50% duty cycle signal generator and method A high frequency, current mode, single-ended-to-differential signal converter with low input impedance constant to very high frequencies and a balanced output signal even for large signals. A wide range of input voltages may be accommodated and a d.c. off... | 04/20/1999 |
| 5543742 | Phase shifting circuit A phase shifting circuit has an oscillation circuit. The oscillation circuit is provided with a charging and discharging capacitor at which the oscillation signal is generated. The oscillation signal has a constant level period and a saw tooth wave period... | 08/06/1996 |
| 5489869 | Antenna control unit attenuator and Bi-phase modulator An apparatus and method for performing spatial nulling in antenna electronics that provides an integrated solution of signal attenuation and bi-phase modulation. One implementation is comprised of load resistors and field-effect-transistors in a gallium a... | 02/06/1996 |
| 5434523 | Circuit and method for adjusting a pulse width of a signal The present invention provides an output signal whose pulse width may be adjusted with respect to the pulse width of an incoming input signal. In particular, a plurality of signals is generated in response to the input signal. One of the plurality of sign... | 07/18/1995 |
| 5243240 | Pulse signal generator having delay stages and feedback path to control delay time A pulse signal generator comprising a plurality of stages of delay gates connected in series for receiving an input pulse signal and generating an output pulse signal, each stage consists of a differential connection circuit and an emitter follower circui... | 09/07/1993 |
| 5157276 | Low jitter clock phase adjust system A low jitter clock phase adjust system divides an input clock signal into three clock signals having precisely equal phase differences from each other. The three clock signals are converted into current vectors and input to a trio of two-quadrature multip... | 10/20/1992 |
| 4935701 | Phase shift circuit A phase shift circuit used in a regenerating repeater, includes a separating unit for separating an input signal into two separate signals having a phase difference of a phase angle of 90° therebetween, one separated signal having a "0" phase and the oth... | 06/19/1990 |