Class 327/245 - Having multiple outputs

Subclass of Class 327 - Miscellaneous active electrical nonlinear devices, circuits, and systems
Definition: Subject matter wherein more than one output is produced.
No. of patents: 21
Last issue date: 07/22/2008

Number	Title	Issue Date
7403054	Sub-picosecond multiphase clock generator A circuit apparatus and method for generating multiphase clocks in a delay lock loop (DLL) at sub-picosecond granularity. The circuit and method of the invention involves locking a number of cycles M in an N stage DLL, e.g., M cycles, where M is an prime number, whi...	07/22/2008
6768356	Apparatus for and method of implementing time-interleaved architecture In accordance with a preferred embodiment, a time-interleaved (or multi-phase) architecture is provided having individual control of a plurality of output signals or phases. The time-interleaved architecture may be implemented using a first set of delay cells such a...	07/27/2004
6680639	Phase shifting arrangement for generating mutually orthogonal signals The present invention is directed to a phase shifting arrangement for generating a set of mutually orthogonal signals. In one aspect, the invention provides a system that includes a phase shifting unit for receiving an input signal. The phase shifting uni...	01/20/2004
6664835	Phase splitter A phase splitter. The splitter includes a transistor having a gate receiving an input signal, a drain and source outputting a first and second output signal with a first and second phase, respectively, a current source providing a current flowing from the...	12/16/2003
6583658	Balanced circuit arrangement The invention relates to a balanced circuit arrangement for converting an asymmetric analogous input signal (S1) into a symmetrical output signal (S2, S3). A first amplifier (2) is provided, whereby the non-inverting input thereof is connected to the anal...	06/24/2003
6294938	System with DLL A system (50) has a shifting delay circuit (60) which provides a variable delay for delaying a source clock and a delay locked loop (DLL) (70) which includes a delay line (72) which provides a variable delay for delaying the source clock. The delay line (...	09/25/2001
6275084	Phase modulated input/output circuit A circuit is designed with a delay circuit (300,301,500) coupled to receive a bias (256) and a reference signal (242). The delay circuit produces a series of phase signals (214). The phase signals are spaced apart in time in response to the bias. Each pha...	08/14/2001
6172542	Selectable single ended-to differential output adjustment scheme A circuit comprising an input circuit and an adjustable delay. The input circuit may be configured to generate a differential signal in response to a single ended signal. The adjustable delay may be configured (i) delay or not change a rising edge or (ii)...	01/09/2001
6140854	System with DLL A system (50) has a shifting delay circuit (60) which provides a variable delay for delaying a source clock and a delay locked loop (DLL) (70) which includes a delay line (72) which provides a variable delay for delaying the source clock. The delay line (...	10/31/2000
6052011	Fractional period delay circuit A fractional period delay circuit to delay a clocking signal by a non-integer fraction of the period of the clocking signal is disclosed. The fractional period delay circuit has a first delay line connected to a master timing signal to delay the master cl...	04/18/2000
6049240	Logical delaying/advancing circuit used An oscillating means having an oscillator outputs a reference clock, and a frequency-dividing means sequentially frequency-dividing the reference clock into a half frequency. A temperature correction data creating means detects a temperature, calculates l...	04/11/2000
5801566	System clock generating circuit for a semiconductor device According to the present invention, when a semiconductor device is tested, a signal for test can be set in the semiconductor device at a desired timing. A second delay circuit of the present invention has the same structure as a first delay circuit in a p...	09/01/1998
5663668	Semiconductor integrated circuit device In an internal clock signal generation circuit, a plurality of internal clock signals of different phases are generated based on an external clock signal. The internal clock signals are synchronized with the external clock signal by a PPL circuit. The plu...	09/02/1997
5592113	Gradual frequency changing circuit An error-limiting circuit for regulating the time required to bring the output signal of a control system such as a phase-locked loop device into conformance with a reference input signal. For a phase-locked loop system the error-limiting circuit is a pha...	01/07/1997
5230013	PLL-based precision phase shifting at CMOS levels A circuit for generating precise, phase shifted, CMOS level output signals with respect to an input data signal has been provided. The circuit utilizes a phase-locked loop for generating a precise clock signal. This precise clock signal is then utilized t...	07/20/1993
5184027	Clock signal supply system A clock signal supply system provides for automatic accurate phase adjustment of clock signals. The system includes an oscillator that produces clock signals and a reference generator that generates a reference signal that has a predetermined relationship...	02/02/1993
5148113	Clock phase alignment A phase error integrator for determining the phase error between a data signal and a clock signal frequency locked to the data signal has a data input and a clock input. In one embodiment the phase error integrator is formed as two functional components, ...	09/15/1992
5140174	Symmetric edge true/complement buffer/inverter and method therefor The present invention is directed to a buffer/inverter which generates symmetric and complementary output signals from a single input signal. The device employs four inverters having similar switching speeds. The true output signal is generated by passing...	08/18/1992
4794275	Multiple phase clock generator A multiple phase clock generator includes a ring of an even number of phase cells, each phase cell generating a separate phased clock signal. Each phase cell supplies its phased clock signal and a prebias output signal in response to concurrent assertion ...	12/27/1988
4760280	Process and apparatus for the synchronization of square signals A process and apparatus for improving the resolution of square, subdivided signals by synchronizing the signals with an auxiliary clock signal. The signals are further conditioned by switching logic elements which, in dependence upon adjacent signals in t...	07/26/1988
4347480	Magnetic resonance gyro phase shifter A phase shifter of a signal processor which involves separation of the cell signals from a magnetic resonance gyro (MRG) using phase locked loops that also serve as frequency multipliers, phase shifting one cell output to maintain phase comparisons within...	08/31/1982

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Class 327/245 - Having multiple outputs