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| Number | Title | Issue Date |
| 7880507 | Circular edge detector A circular edge detector on an integrated circuit including a plurality of edge detector cells, each of the plurality of edge detector cells having an input select block operable to receive a data signal and a previous cell signal and to generate a present cell sign... | 02/01/2011 |
| 7855582 | Device and method for detecting a timing of an edge of a signal with respect to a predefined edge of a periodic signal A device and method for detecting timing of an edge of a signal with respect to a timing of a predefined edge of a periodic signal is provided, wherein the edge defines a state change between a first state and a second state of the signal, and wherein the device can... | 12/21/2010 |
| 7782093 | Integrated circuit and method of detecting a signal edge transition The invention relates to an edge transition detector, and a method of operating an edge transition detector. An integrated circuit includes an edge transition detector for producing an output signal at an output node in response to an input signal. The edge transiti... | 08/24/2010 |
| 7759980 | Circular edge detector for measuring timing of data signals A circular edge detector on an integrated circuit including a plurality of edge detector cells, each of the plurality of edge detector cells having an input select block operable to receive a data signal and a previous cell signal and to generate a present cell sign... | 07/20/2010 |
| 7436919 | Methods and apparatus for bit synchronizing data transferred across a multi-pin asynchronous serial interface Methods, devices and systems are provided for bit synchronizing multiple serial bitstreams (106) with a common clock signal (116). Activity occurring in each bitstream is detected (304) for each of a plurality of phases corresponding to cycles o... | 10/14/2008 |
| 7432742 | System and method for detecting an edge of a data signal A system and method for detecting an edge of a data signal carried on an observability bus. In one embodiment, a first performance counter is connected to receive the data signal in order to assert a trigger signal in response to detecting an assertion of the data s... | 10/07/2008 |
| 7414438 | Clock based voltage deviation detector The clock based voltage deviation detector of the present invention includes a pulse module, an indicator module and a correlation module. The pulse module generates a stream of reset pulses as a function of a clock signal. The indicator module generates a pass/fail... | 08/19/2008 |
| 7403044 | Method of producing balanced data output Strobe signals are coupled to a phase detector which compares rising and falling edges of the respective strobe signals. If the phase detector determines that there is a mismatch, it outputs an UP or DOWN control signal to a control circuit. The control circuit then... | 07/22/2008 |
| 7362657 | Aquatic object detection and disruption system A system includes a receive line array that generates one or more receive line array signals, a processor operatively connected to the receive line array to process the receive line array signals and to generate detonation signals based upon the processed receive li... | 04/22/2008 |
| 7362186 | Phase-locked loop circuit and data reproduction apparatus This invention relates to a phase-locked loop circuit and a data reproduction apparatus, which can reduce a processing time that is required for initial adjustment in the data reproduction apparatus. In a digital data reproduction apparatus having two control functi... | 04/22/2008 |
| 7352167 | Digital trigger An improved digital trigger circuit has a plurality of data samples extracted from an input electrical signal for each sample clock cycle. The plurality of data samples are compared in parallel with a high threshold level and a low threshold level which provides hys... | 04/01/2008 |
| 7288969 | Zero clock delay metastability filtering circuit A metastability filtering circuit comprising: a sampling circuit for sampling a first clock signal with a second clock signal to produce a sampled first clock signal, the first clock signal being synchronous to an interface between first and second systems; an edge ... | 10/30/2007 |
| 7280629 | Method and apparatus for receiving data based on tracking zero crossings Conventional receiver architectures are based on either frequency/phase tracking or oversampling. Both receiver types typically employ sensitive analog circuits, which create noise, consume power and utilize valuable space in their implementation. The invention adop... | 10/09/2007 |
| 7276980 | Phase-locked loop circuit and data reproduction apparatus This invention relates to a phase-locked loop circuit and a data reproduction apparatus, which can reduce a processing time that is required for initial adjustment in the data reproduction apparatus. In a digital data reproduction apparatus having two control functi... | 10/02/2007 |
| 7271579 | AC signal level detection circuit An AC voltage generated by an AC power source 1 is rectified by a full-wave rectifying circuit 2, which generates a rectified voltage. An internal regulator 33 performs waveform shaping of the rectified voltage. A comparator 42 compares t... | 09/18/2007 |
| 7242219 | Circuit for parity tree structure A circuit for a parity tree is disclosed. In one embodiment, a circuit for a parity tree includes a pull-up circuit, a pull-down circuit, and a cross-couple circuit. The circuit, an XOR/XNOR circuit, includes both an output node and an inverted output node. For a gi... | 07/10/2007 |
| 7191079 | Oscilloscope having advanced triggering capability An advanced trigger circuit includes two trigger decoders, each triggering on one of respective pluralities of continuous-time trigger events. In one embodiment, a programmable timer begins timing in response to an output signal of the first trigger decoder and gene... | 03/13/2007 |
| 7176979 | Synchronization pulse detection circuit A synchronization pulse detector includes an absolute value independent shape detector for processing samples of an input signal having a synchronization pulse and a plurality of non-synchronization pulses to determine whether such samples have a predetermined seque... | 02/13/2007 |
| 7129757 | Clock frequency detect with programmable jitter tolerance An apparatus and method is disclosed for programmable determination of frequency, phase, and jitter relationship of a first clock and a second clock in an electronic system. In a first, initialization, mode, a first register and a second register are initialized wit... | 10/31/2006 |
| 7113562 | Method and apparatus for receiving data based on tracking zero crossings Conventional receiver architectures are based on either frequency/phase tracking or oversampling. Both receiver types typically employ sensitive analog circuits, which create noise, consume power and utilize valuable space in their implementation. The invention adop... | 09/26/2006 |
| 7109475 | Leading edge/trailing edge TOF detection Disclosed are a time-of-flight mass spectrometer and signal processing electronics. The signal processing electronics include a plurality of time-to-digital converters configured to receive signal pulses from the same detector anode within the time-of-flight mass sp... | 09/19/2006 |
| 7106116 | Pulse duty deterioration detection circuit A pulse duty deterioration detection circuit with a high monitoring precision is easily provided. The pulse duty deterioration detection circuit comprises a delay circuit comprised of a general-purpose gate circuit which generates a delayed synchronous to-be-monitor... | 09/12/2006 |
| 7098715 | Programmable dual-edge triggered counter A counter for synthesizing clock signals with minimal jitter analyzes an ongoing count to determine whether the rising edge of an output clock should be triggered by the rising edge or falling edge of an input clock signal and to further determine whether the fallin... | 08/29/2006 |
| 7071748 | Charge pump clock for non-volatile memories A charge pump clock for a memory device wherein pump clock signals are generated at an adaptive rate. The circuit of the present invention generates clock edges at a minimum of TD seconds apart so long as address transitions do not exceed a pre-determined... | 07/04/2006 |
| 7034622 | Phase-locked loop circuit and data reproduction apparatus This invention relates to a phase-locked loop circuit and a data reproduction apparatus, which can reduce a processing time that is required for initial adjustment in the data reproduction apparatus. In a digital data reproduction apparatus having two control functi... | 04/25/2006 |
| 7026842 | Method and apparatus for reliable pulse event detection A circuit for detecting asynchronous events includes a first event detection latch; and a second event detection latch coupled to the first event detection latch, wherein the first event detection latch is ready to detect an event when the second event detection lat... | 04/11/2006 |
| 7015726 | Edge detector and method Embodiments of an edge detector and related methods are disclosed. One method embodiment for detecting the rising and/or falling edge of an input clock signal of unknown phase and frequency includes providing a reference clock signal of a known phase and frequency t... | 03/21/2006 |
| 7009428 | High speed source synchronous signaling for interfacing VLSI CMOS circuits to transmission lines A system of the present invention uses small swing differential source synchronous voltage and timing reference (SSVTR and /SSVTR) signals to compare single-ended signals of the same slew rate generated at the same time from the same integrated circuit for high freq... | 03/07/2006 |
| 6993105 | Linearized digital phase-locked loop A method of synchronizing a clock signal to a data signal, comprising the steps of (A) detecting a first edge of the data signal and a position of the first edge, (B) determining if the position is within a zone, (C) if the edge is not within the zone, adjusting the... | 01/31/2006 |
| 6950484 | Linearized digital phase-locked loop method A method for synchronizing a clock signal to a data signal, comprising the steps of (A) detecting an edge of the data signal, (B) determining whether a position of the edge is within a zone and (B) if the edge is not within the zone, adjusting the clock signal towar... | 09/27/2005 |
| 6950486 | Delay apparatus and method A delay apparatus delays a rising edge and a falling edge of a digital signal. The delay apparatus includes a first edge detection circuit which detects a first edge or rising edge of the digital signal and generates a detection signal; a set circuit that includes a... | 09/27/2005 |
| 6885221 | Signal detection apparatus, signal detection method, signal transmission system, and computer readable program to execute signal transmission In a differential output signal circuit suitable for restraining voltage overshooting/undershooting at differential output terminals due to lags in input signals and realizing stable and fast switching of differential input signals, a first differential pair of PMOS... | 04/26/2005 |
| 6870402 | Transition-aware signaling An improved receiver circuit for use on an integrated chip is disclosed. The receiver circuit is interposed in an interconnect line between electrical components in an integrated circuit. The receiver circuit has a transition detection circuit that generates a trans... | 03/22/2005 |
| 6828865 | Phase-locked loop circuit and data reproduction apparatus This invention relates to a phase-locked loop circuit and a data reproduction apparatus, which can reduce a processing time that is required for initial adjustment in the data reproduction apparatus. In a digital data reproduction apparatus having two control functi... | 12/07/2004 |
| 6753705 | Edge sensitive detection circuit An edge sensitive detection circuit includes a filter module and a soft latch module. The filter module is operably coupled to receive an input logic signal that corresponds to the triggering of an event and produces a pulse signal in response to an edge of the inpu... | 06/22/2004 |
| 6711226 | Linearized digital phase-locked loop A method of synchronizing a clock signal to a data signal, comprising the steps of (A) detecting a first edge of the data signal, (B) determining a first value indicating a position of the first edge, (C) adding the first value to a second value, wherein the second ... | 03/23/2004 |
| 6636080 | Apparatus for detecting edges of input signal to execute signal processing on the basis of edge timings An apparatus for detecting an edge timing of an input signal and operating on the basis of the edge timing while power consumption thereof is reduced. The apparatus includes an edge detecting circuit that detects edges of an input signal to generate an ed... | 10/21/2003 |
| 6535023 | Linearized digital phase-locked loop method A method of synchronizing a clock signal to a data signal, comprising the steps of (A) detecting a first edge of the data signal, (B) determining a first value indicating a position of the first edge, (C) adding the first value to a second value, wherein ... | 03/18/2003 |
| 6377082 | Loss-of-signal detector for clock/data recovery circuits A loss-of-signal (LOS) detector, for example, for a clock/data recovery (CDR) circuit for an optical fiber communication system, has (1) a transition detector for detecting stuck-on-one and stuck-on-zero LOS conditions and (2) an inconsistency detector fo... | 04/23/2002 |
| 6348822 | Semiconductor storage device capable of speeding up an access from a standby state In a semiconductor storage device, in a CE access stage, an access operation is executed by generating a reference pulse CLK_NEW by only a signal (node A) generated through the detection of a change of the CE signal by means of a CE transition detection c... | 02/19/2002 |
