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Pillow with retractable umbrella
A pillow assembly having a supporting assembly and a retractable umbrella assembly that is easily transportable and allows a user to support his/her head while covering their face from sunlight.
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| Number | Title | Issue Date |
| 7952409 | Clock generation circuit and integrated circuit A clock generation circuit comprises: a first generation unit; a second generation unit; and a control unit that, using a plurality of third delay elements that respectively have a propagation delay time that correlates with the propagation delay time of a first del... | 05/31/2011 |
| 7855588 | Clock signal generation apparatus A clock signal generation apparatus containing variable delay devices for varying the delay time of two-phase clock signals used in a load circuit that uses non-overlap clock signals; a non-overlap detector for detecting a non-overlap time in the H-level zones of th... | 12/21/2010 |
| 7612595 | Sequence independent non-overlapping digital signal generator with programmable delay A circuit for generating non-overlapping clock signals includes a programmable delayed reference clock signals circuit to produce a plurality of delayed reference clock signals and a plurality of delay clock signal generators, operatively connected to the programmab... | 11/03/2009 |
| 7459952 | Clock signal generating device, generating method, and signal processing device When the operating speed of a switched capacitor circuit is accelerated, the timing of the clock signals regulating switched capacitor circuit operation can be disrupted by the effects of variation introduced by the manufacturing process as well as parasitic resista... | 12/02/2008 |
| 7352222 | Clock generator with programmable non-overlapping-clock-edge capability A system and method for generating and optimizing clock signals with non-overlapping edges on a chip using a unique programmable on-chip clock generator. Overlapping of the edges of the clocking signals is avoided by adjusting an amount of delay introduced in the on... | 04/01/2008 |
| 7330062 | Input/output logical circuit A logical circuit receives first and second input signals in which a period of a first logic level partially overlaps, and outputs first and second output signals in which a period of the first logic level does not overlap. The logical circuit comprises a first unit... | 02/12/2008 |
| 7274228 | Method and apparatus for digital phase generation at high frequencies An apparatus and method for generating phase related clocks, includes delaying a clock input by a cycle delay magnitude to generate a cycle delay signal and N delay taps is disclosed. Each delay tap has a delay equal to a fractional amount of the cycle delay magnitu... | 09/25/2007 |
| 7265690 | Simplified data recovery from high speed encoded data The present invention facilitates data recovery without requiring selection of a sample phase. The data is recovered by sampling a received signal to obtain a number of samples at a number of phases over a given time period referred to as a bit time. The samples are... | 09/04/2007 |
| 7230495 | Phase-locked loop circuits with reduced lock time PLL circuits are provided in which a voltage-controlled oscillator (VCO) comprising one or more voltage-controlled delay units (VCDs) is initialized with the control voltage of a voltage-controlled delay line (VCDL) having substantially identical VCDs. In general, V... | 06/12/2007 |
| 7230465 | Duty cycle corrector A duty cycle corrector comprising a first circuit and a second circuit. The first circuit is configured to receive a clock signal having a first phase and a second phase and to obtain a first threshold value based on the length of the first phase and part of the sec... | 06/12/2007 |
| 7190204 | Logical circuit A logical circuit receives first and second input signals in which a period of a first logic level partially overlaps, and outputs first and second output signals in which a period of the first logic level does not overlap. The logical circuit comprises a first unit... | 03/13/2007 |
| 7152008 | Calibrated differential voltage crossing In general, in one aspect, the disclosure describes an apparatus for calibrating signals. The apparatus includes a receiver pair to receive a differential signal and a reference signal and to generate at least one comparison signal reflecting where a first signal of... | 12/19/2006 |
| 7145376 | Method and circuitry for reducing duty cycle distortion in differential delay lines A method and circuitry are provided for reducing duty cycle distortion in differential solid state delay lines. The differential solid state delay lines of the present invention include a plurality of delay line cells or stages connected in series. Because there may... | 12/05/2006 |
| 7139842 | Method and apparatus for intersystem cut/copy and paste An apparatus in accordance with the invention includes a switch-box, where the switch-box includes a memory buffer to which information is copied from a computing system selected via the switch-box from two or more computing systems coupled with the switch-box as a ... | 11/21/2006 |
| 7096443 | Method for determining the critical path of an integrated circuit A method of determining the critical path of a circuit includes first determining the paths, their mean path transit times and their path transit time fluctuations. Paths having similar statistical parameters are combined to form one path group. For each path group,... | 08/22/2006 |
| 7034595 | Multi-phase clock signal generators and methods of generating multi-phase clock signals A multi-phase clock signal generator provides multiple clock signals from an input clock signal, the multiple clock signals being inverted from one another and having substantially the same delay and duty cycle characteristics. Methods of generating multiple clock s... | 04/25/2006 |
| 7005891 | Data transmission circuit for universal serial bus system The data transmission circuit generates the first and second data signals that are transferred respectively to first and second data lines after delaying or expanding a rising edge or a falling edge of an externally supplied data input signal, so that a crossover vo... | 02/28/2006 |
| 6965272 | Worldwide marketing logistics network including strategically located centers for frequency programming crystal oscillators to customer specification A worldwide logistics network includes a processing center for receiving customer orders for crystal oscillators over communications links, processing the orders, and generating work orders that are selectively disseminated over communications links to programming c... | 11/15/2005 |
| 6964002 | Scan chain design using skewed clocks A scan chain comprising a series of flip-flops and two clock signals, where each clock signal is coupled to alternating flip-flops in the series. The second clock signal is typically 180 degrees out of phase with the first clock signal. The two clock signals may be ... | 11/08/2005 |
| 6954113 | Programmable oscillator circuit A programmable crystal oscillator is provided having a memory for storing frequency-defining parameters. Typically, one of these parameters is used to program an adjustable capacitive load circuit coupled to a crystal to thereby adjust the crystal source frequency. ... | 10/11/2005 |
| 6946889 | Self alignment system for complement clocks A self-alignment system for complement clock signals includes a first delay circuit and a second delay circuit. A first clock signal may be propagated through the first delay circuit and a second clock signal may be propagated through the second delay circuit. A pro... | 09/20/2005 |
| 6928128 | Clock alignment circuit having a self regulating voltage supply Clock alignment circuits and techniques for reducing power dissipation, increasing power supply noise immunity, decreasing process and temperature variation sensitivity, and providing a wide operating range. A power supply generator generates an isolated supply volt... | 08/09/2005 |
| 6922097 | Asymmetric-amplitude dual-polarity charge pump with four-phase selectable operation A symmetric dual-voltage charge pump and its control circuit generate bipolar output voltages. The charge pump converts a unipolar power source to a set of dual-voltage outputs of opposite polarity that are completely independent of each other. The charge pump inclu... | 07/26/2005 |
| 6900682 | Clock generator with programmable non-overlapping-clock-edge capability A system and method for generating and optimizing clock signals with non-overlapping edges on a chip using a unique programmable on-chip clock generator. Overlapping of the edges of the clocking signals is avoided by adjusting an amount of delay introduced in the on... | 05/31/2005 |
| 6815994 | Method of scaling digital circuits and controlling the timing relationship between digital circuits A phase splitter is formed by first and second branches that generate respective first and second complimentary output clock signals from an input clock signal. The first branch includes two series connected inverters, the first of which receives the input clock sig... | 11/09/2004 |
| 6798248 | Non-overlapping clock generation According to some embodiments, non-overlapping clocks are to be generated. ... | 09/28/2004 |
| 6710637 | Non-overlap clock circuit In a non-overlap clock generator circuit providing two-phase clock signals, the clock-to-Q delay of memory elements is used to define the non-overlap times. The non-overlap time can be programmed in increments of the clock-to-Q delay of a standard memory element. | 03/23/2004 |
| 6653881 | Clock generator with programmable non-overlapping-clock-edge capability A system and method for generating and optimizing clock signals with non-overlapping edges on a chip using a unique programmable on-chip clock generator. Overlapping of the edges of the clocking signals is avoided by adjusting an amount of delay introduce... | 11/25/2003 |
| 6489826 | Clock generator with programmable non-overlapping clock-edge capability A system and method for generating and optimizing clock signals with non-overlapping edges on a chip using a unique programmable on-chip clock generator. Overlapping of the edges of the clocking signals is avoided by adjusting an amount of delay introduce... | 12/03/2002 |
| 6480048 | Circuit for generating an inverse signal of a digital signal with a minimal delay difference between the inverse signal and the digital signal Circuit for generating an inverse signal of a digital signal with minimal delay difference between the inverse signal and the digital signal. Two inverter circuits (6, 8; 7, 9) have been connected in series. The output signal of the second inverter circui... | 11/12/2002 |
| 6456138 | Method and apparatus for a single upset (SEU) tolerant clock splitter A clock splitter circuit for providing a single event upset (SEU) tolerant clock signal to latches in a space-based environment. The clock splitter circuit can include one or more event offset circuit delay circuits. The event offset delay receives a cloc... | 09/24/2002 |
| 6420920 | Method and apparatus for phase-splitting a clock signal A phase splitter is formed by first and second branches that generate respective first and second complimentary output clock signals from an input clock signal. The first branch includes two series connected inverters, the first of which receives the inpu... | 07/16/2002 |
| 6380783 | Cyclic phase signal generation from a single clock source using current phase interpolation A system and corresponding method for generating multiple phases within a single clock cycle of an input signal is disclosed. The method includes the steps of generating a plurality of output signals from an input source signal, where each of the pluralit... | 04/30/2002 |
| 6353340 | Input and output circuit with reduced skew between differential signals A differential-signal input and output circuit receives a pair of differential signals, and changes and outputs the pair of differential signals at almost the same time at timing when whichever changes last changes. In another differential-signal input an... | 03/05/2002 |
| 6327191 | Address signal generator in a semiconductor memory A semiconductor memory includes a control signal generator for generating a first control signal, a second control signal, and a third control signal; a first inverter for receiving an external address in accordance with the first control signal; a latch ... | 12/04/2001 |
| 6323711 | Clock generator with programmable non-overlapping-clock-edge-capability A system and method for generating and optimizing clock signals with non-overlapping edges on a chip using a unique programmable on-chip clock generator. Overlapping of the edges of the clocking signals is avoided by adjusting an amount of delay introduce... | 11/27/2001 |
| 6307416 | Integrated circuit for producing two output clock signals at levels which do not overlap in time The integrated circuit has two inputs each supplying one input clock. Two outputs each output one output clock. The first logic levels of the output clock signals at the outputs do not overlap in time.... | 10/23/2001 |
| 6275084 | Phase modulated input/output circuit A circuit is designed with a delay circuit (300,301,500) coupled to receive a bias (256) and a reference signal (242). The delay circuit produces a series of phase signals (214). The phase signals are spaced apart in time in response to the bias. Each pha... | 08/14/2001 |
| 6172542 | Selectable single ended-to differential output adjustment scheme A circuit comprising an input circuit and an adjustable delay. The input circuit may be configured to generate a differential signal in response to a single ended signal. The adjustable delay may be configured (i) delay or not change a rising edge or (ii)... | 01/09/2001 |
| 6163194 | Integrated circuit with hardware-based programmable non-overlapping-clock-edge capability A system and method for generating and optimizing clock signals with non-overlapping edges on a chip using a unique programmable on-chip clock generator. Overlapping of the edges of the clocking signals is avoided by adjusting an amount of delay introduce... | 12/19/2000 |
