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| Number | Title | Issue Date |
| 8183904 | Control system for a phase generator and corresponding control method A control system for a phase generator including a delay block including delay units, and first and second multiplexers configured to receive output signals of each of the delay units and to respectively supply first and second output signals. The control system may... | 05/22/2012 |
| 7932763 | Signal processing circuit and signal processing method A signal processing circuit includes: a first operation circuit for receiving a phase component of an input signal, and generating an adjusted phase component and at least one weighting factor according to the phase component of the input signal; a second operation ... | 04/26/2011 |
| 7388412 | Clock multipliers using filter bias of a phase-locked loop and methods of multiplying a clock A clock multiplier includes a phase-locked loop (PLL), a bias generator, a counter, a selection circuit, a flip-flop, a phase comparator, a delay controller and a variable delay circuit. The variable delay circuit, which is biased by a delay cell bias signal, delays... | 06/17/2008 |
| 7339364 | Circuit and method for on-chip jitter measurement An improved built-in self-test (BIST) circuit and an associated method for measuring phase and/or cycle-to-cycle jitter of a clock signal, the BIST circuit implement a Variable Vernier Digital Delay Locked Line method. Specifically, the embodiments of the BIST circu... | 03/04/2008 |
| 7333390 | Phase controlled high speed interfaces A system and method are used to allow high speed communication between a chip and an external device. The system and method include a PLL with multiple phased outputs configured to be controlled digitally, a deskew PLL configured to align a clock of controller circu... | 02/19/2008 |
| 7327173 | Delay-locked loop having a pre-shift phase detector A clock generator for generating an output clock signal synchronized with an input clock signal having first and second adjustable delay lines. The first adjustable delay lines is adjusted following initialization of the clock generator to expedite obtaining a lock ... | 02/05/2008 |
| 7327819 | Phase detectors in carrier recovery for offset QAM and VSB A carrier recovery, symbol timing, and carrier phase tracking systems and methods suitable for use in connection with a dual-mode QAM/VSB receiver system. In-phase signals are sampled twice a symbol at the in-phase symbol sampling time and at the quadrature-phase sy... | 02/05/2008 |
| 7289381 | Programmable boosting and charge neutralization A programmable capacitance circuit including an input node; an output node; and a plurality of capacitance stages. Each of the capacitance stages is coupled to the input node and the output node, and wherein each capacitance stage is configured to be switched into a... | 10/30/2007 |
| 7157951 | Digital clock manager capacitive trim unit A delay line for a digital clock manager includes a tap delay structure and a trim delay structure. The trim delay structure includes a first buffer coupled to receive a clock signal from the tap delay structure, and in response, provide a delayed clock signal to a ... | 01/02/2007 |
| 7106117 | Delayed clock signal generator A device which may be configured to generate delayed clock signals by a specified phase difference, which may include a clock generator circuit for generating at least one clock signal, a delayed clock signal generator for delaying the at least one clock signal, a p... | 09/12/2006 |
| 7095801 | Phase adjustable polyphase filters A polyphase filter for wireless communication systems includes at least two phase splitting filters each having a variable resistance across their respective outputs. The variable resistance can take any suitable form, such as a MOS transistor biased in the linear (... | 08/22/2006 |
| 7088156 | Delay-locked loop having a pre-shift phase detector A clock generator for generating an output clock signal synchronized with an input clock signal having first and second adjustable delay lines. The first adjustable delay lines is adjusted following initialization of the clock generator to expedite obtaining a lock ... | 08/08/2006 |
| 7062005 | Master slave frame lock method The present invention relates to a system for synchronising slave and master timing, comprising a phase adjust circuit for receiving and delaying an arbitrary clock signal by an adjustable amount and outputting a delayed clock signal related to the slave timing, and... | 06/13/2006 |
| 7053732 | Multi-bit time delay adjuster unit for high RF applications and method A multi-bit time-delay adjuster with Radio Frequency (RF) MicroElectroMechanical (MEM) switches may be used in MultiCarrier Power Amplifiers (MCPAs) with a feed-forward linearization technique. The multi-bit time-delay adjuster makes it possible to automatically con... | 05/30/2006 |
| 7042265 | Interlaced delay-locked loops for controlling memory-circuit timing For control, some memory circuits use a delay-locked loop to generate a set of signals, each delayed a different amount relative a reference signal. However, as circuits get faster and faster, conventional delay-locked loops require use of extra interpolation circui... | 05/09/2006 |
| 7038517 | Timing vernier using a delay locked loop A method for synchronizing a plurality of programmable timing verniers with a reference pulse signal, each of the verniers being programmable to one of a plurality of timing steps within a delay range determined by a control signal applied to a bias input. A first a... | 05/02/2006 |
| 6982578 | Digital delay-locked loop circuits with hierarchical delay adjustment Fine tuned signal phase adjustments are provided by multiple cascaded phase mixers. Each phase mixer outputs a signal having a phase between the phases of its two input signals. With each subsequent stage of phase mixers, the signals generated by the phase mixers ha... | 01/03/2006 |
| 6903591 | Phase shifter circuit A phase shift circuit that generates a phase shift signal whose amplitude matches at a plurality of frequencies without increasing the circuit area. The phase shifter circuit includes first and second differential amplifiers which generate first and second first pha... | 06/07/2005 |
| 6853231 | Timing vernier using a delay locked loop A method for synchronizing a plurality of programmable timing verniers with a reference pulse signal, each of the vernier being programmable to one of a plurality of timing steps within a delay range and the delay range being determined by a control signal applied t... | 02/08/2005 |
| 6737897 | Power reduction for delay locked loop circuits A delay locked loop circuit includes a plurality of delay cells connected in series. Each of the delay cells connects to an input node which provides a clock signal. A shift register selects one of the delay cells to allow the clock signal to enter the selected dela... | 05/18/2004 |
| 6674314 | Interpolating circuit, DLL circuit and semiconductor integrated circuit Disclosed is an interpolating circuit for producing an output signal having a delay time corresponding to a value obtained by performing interior division of a phase difference between entered first and second signals by a preset interior division ratio. ... | 01/06/2004 |
| 6646484 | PLL circuit including a control logic circuit for adjusting the delay times of the clocks so that the phase error of the clocks is reduced VDLs and delay an input clock and a return clock and provide a delayed input clock and a delayed return clock to a PLL part. The PLL part receives the delayed input clock and the delayed return clock, and outputs a PLL output so that these signals are syn... | 11/11/2003 |
| 6608509 | Semiconductor integrated circuit device and microcomputer A semiconductor integrated circuit include a logic circuit which is formed of p-channel MIS transistors and n-channel MIS transistors, a first oscillation circuit of variable oscillation frequency which is formed of p-channel MIS transistors and n-channel... | 08/19/2003 |
| 6593821 | Frequency controlled oscillator An oscillator generates an oscillation signal, and a phase shifter outputs a phase shift oscillation signal corresponding to a difference between a frequency of the oscillation signal and a target frequency. A multiplier outputs a multiplied signal corres... | 07/15/2003 |
| 6586983 | Signal phase adjustment circuit to set optimum phase A signal phase adjustment circuit to set an optimum phase by adjusting the difference in delay times between signal lines even when the distribution of the amount of phase modification that can be received normally is divided into a plurality of continuou... | 07/01/2003 |
| 6586979 | Method for noise and power reduction for digital delay lines A delay circuit that includes a plurality of delay cells connected in series. Each of the delay cells connects to an input node which provides a clock signal. A shift register selects one of the delay cells to allow the clock signal to enter the selected ... | 07/01/2003 |
| 6441664 | Signal phase adjustment circuit to set optimum phase A signal phase adjustment circuit to set an optimum phase by adjusting the difference in delay times between signal lines even when the distribution of the amount of phase modification that can be received normally is divided into a plurality of continuou... | 08/27/2002 |
| 6437618 | Delay locked loop incorporating a ring type delay and counting elements Disclosed is a delay locked loop for use in a semiconductor memory device, for operating in low clock frequency applications that require a small chip size. The delay locked loop includes an input unit for receiving an external clock signal from which a c... | 08/20/2002 |
| 6404248 | Delay locked loop circuit for synchronizing internal supply clock with reference clock A DLL circuit has edge detecting/phase comparing portion 2 that generates an original comparison signal that is set to logic "1" when the rise-up of feedback clock FBCLK is prior to the rise-up of reference clock RCLK, and also set to logic "0" when: the ... | 06/11/2002 |
| 6400200 | Semiconductor integrated circuit which generates waveforms which are out of phase with each other A semiconductor integrated circuit comprises a phase control unit for shifting the phase of an input signal by two or more different fixed phases so as to generate two or more output signals out of phase. A phase detector detects phase differences among t... | 06/04/2002 |
| 6388485 | Delay-locked loop circuit having master-slave structure A delay-locked loop (DLL) circuit having a master-slave structure wherein the DLL circuit includes a master delay loop and a slave stage. The master delay loop delays an external clock signal by a predetermined delay time and generates a feedback signal w... | 05/14/2002 |
| 6377092 | Delay locked loop circuit capable of adjusting phase of clock with high precision A DLL circuit includes a fine delay circuit including a first inverter circuit, a second inverter circuit and delay units. The first inverter circuit has an output terminal connected to an output terminal of the second inverter and the first and second in... | 04/23/2002 |
| 6356131 | 90-degree phase shifter There is disclosed a 90-degree phase shifter so configured that an input signal is supplied through a variable gain amplifying circuit and a phase adjusting circuit to a low pass filter and also supplied through another variable gain amplifying circuit an... | 03/12/2002 |
| 6335647 | Skew adjusting circuit A skew adjusting circuit can carry out optimum correction of skew by automatically reading skew amounts of transmission paths with a receiving-side IC, without setting particular skew amounts externally. The skew adjusting circuit includes delay generatin... | 01/01/2002 |
| 6316982 | Digital clock with controllable phase skew A method and apparatus for generating an output clock signal having a frequency fO derived from a reference clock signal having a frequency fR, such that ##EQU1## is satisfied, wherein M and N are integers and M | 11/13/2001 |
| 6313680 | Phase splitter This invention provides a phase splitter device that generates in-phase and quadrature outputs that have a phase difference of substantially a phase set value (e.g., 90°) and an amplitude difference of substantially an amplitude set value (e.g., zero). A... | 11/06/2001 |
| 6300803 | Phase-comparison circuit A phase-comparison circuit includes (a) a first PNP transistor, (b) a second PNP transistor, (c) a third NPN transistor electrically connected to both a collector of the first PNP transistor and a base of the second PNP transistor, and (d) a constant curr... | 10/09/2001 |
| 6229865 | Phase difference detection circuit for liquid crystal display A phase difference detection circuit of a phase locked loop (PLL) for liquid crystal display which compares a phase between external synchronous signal and an internal synchronous signal from the PLL to generate a phase difference detection signal, includ... | 05/08/2001 |
| 6225843 | Semiconductor integrated circuit device A semiconductor integrated circuit device includes a first delay circuit delaying a first clock signal, a second delay circuit delaying a second clock signal which has an inverted phase with respect to the first clock signal, a phase comparator outputting... | 05/01/2001 |
| 6125158 | Phase locked loop and multi-stage phase comparator The disclosure describes a multi-stage phase comparator and a phase-locked loop incorporating such a comparator. The comparator measures a phase difference between a reference signal and an output signal using a periodic clock. The comparator is a two sta... | 09/26/2000 |
