Class 327/225 - With logic element (e.g., NOR gate, etc.)

Subclass of Class 327 - Miscellaneous active electrical nonlinear devices, circuits, and systems
Definition: Subject matter wherein a device performing a Boolean algebraic
No. of patents: 104
Last issue date: 04/26/2011

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Number	Title	Issue Date
7932762	Latch and DFF design with improved soft error rate and a method of operating a DFF A single-path latch, a dual-path latch, a method of operating a DFF and a library of cells. In one embodiment, the single-path latch includes: (1) a passgate coupled to the data input, (2) a feedback path coupled to the passgate, the data output coupled thereto and ...	04/26/2011
7622978	Data holding circuit and signal processing circuit A data holding circuit is capable of latching an input signal at both a rising edge and a falling edge of a clock signal. Several flip-flops and exclusive OR circuits cooperate to achieve this function. ...	11/24/2009
7323909	Automatic extension of clock gating technique to fine-grained power gating A method extends a clock-gating technique to provide a sleep signal for controlling switch circuits that reduce active leakage power. Using this extension of the clock-gating technique, fine-grained power-gating is achieved. The method automatically identifies, at a...	01/29/2008
7292064	Minimizing timing skew among chip level outputs for registered output signals A synchronous output buffer circuit which effectively moves combinational logic associated with an output enable operation, boundary scan operation, and voltage translation to a pipe that leads into a pair of output registers that operate in response to the output c...	11/06/2007
7274235	Electronic circuitry protected against transient disturbances and method for simulating disturbances The circuitry comprises successive stages, each comprising a combinatory logic circuit connected to the input of a first latch. Staggered clock signals are respectively associated with the first latches of the odd and even stages. Means for detecting a transient dis...	09/25/2007
7265589	Independent gate control logic circuitry A dynamic logic gate has a dynamic node pre-charged in response to a pre-charge phase of a clock signal and a logic tree with a plurality of logic inputs for evaluating the dynamic node during an evaluate phase of the clock signal in response to a Boolean combinatio...	09/04/2007
7218159	Flip-flop circuit having majority-logic circuit A flip-flop circuit having a majority-logic circuit is disclosed. The circuit further includes multiple master latches for writing in corresponding input signals, and one slave latch having an input connected to an output of the majority-logic circuit and an output ...	05/15/2007
7212040	Stabilization of state-holding circuits at high temperatures A state-holding circuit having improved stability at high temperatures includes a bi-stable circuit capable of assuming one of two reversible and stable states. The bi-stable circuit comprises a plurality of logic components (e.g., transistors) arranged into two sid...	05/01/2007
7125620	Fuel cell membrane and fuel cell system with integrated gas separation The present invention provides a protonically conductive membrane for use in a direct methanol fuel cell wherein a portion of said protonically conductive membrane conducts protons from the anode face of the membrane to the cathode face of the protonically conductiv...	10/24/2006
7109771	Semiconductor integrated circuit with reduced leakage current A combination circuit is switched between an active state where power is supplied thereto in response to a control signal and an inactive state where power thereto is interrupted. A flip-flop circuit connected to an input terminal of the combination circuit stores a...	09/19/2006
7088162	Circuit generating constant narrow-pulse-width bipolarity monocycles A mono-cycle generating circuit includes a multiplexer, a pulse generating circuit, and a buffer circuit. The multiplexer receives data of a logical 1 or a logical 0, determines whether to generate a positive mono-cycle or a negative mono-cycle, based upon the data,...	08/08/2006
7023235	Redundant single event upset supression system CMOS transistors are configured to operate as either a redundant, SEU-tolerant, positive-logic, cross-coupled Nor Gate SR-flip flop or a redundant, SEU-tolerant, negative-logic, cross-coupled Nand Gate SR-flip flop. The register can operate as a memory, and further ...	04/04/2006
6917236	Method and apparatus for level shifting A level-shifter architecture with high-voltage driving capability and extremely low power consumption, exploiting dynamic control of the charge on the gate electrodes of the high-voltage output transistors, is provided. The architecture can be integrated in CMOS tec...	07/12/2005
6822478	Data-driven clock gating for a sequential data-capture device A circuit for capturing data from a bus having a flip-flop register, comparison logic and clock logic. The comparison logic determines whether any bit on the bus has changed logic state. If a bit has changed state, the comparison logic asserts an enable signal which...	11/23/2004
6791387	Feedback latch circuit and method therefor A feedback latch circuit includes a first logic OR gate for performing a logic OR operation upon a clock input signal and a latch output, a first logic AND gate for performing a logic AND operation upon output of the first logic OR gate and a data input signal, a se...	09/14/2004
6731151	Method and apparatus for level shifting A level-shifter architecture with high-voltage driving capability and extremely low power consumption, exploiting dynamic control of the charge on the gate electrodes of the high-voltage output transistors, is provided. The architecture can be integrated in CMOS tec...	05/04/2004
6657472	Circuit, system, and method for programmably setting an input to a prioritizer of a latch to avoid a non-desired output state of the latch The present invention includes a circuit, system, and method for avoiding a non-desired output from a latch, and a selector circuit that is programmable to select an input to a prioritizer which, based on that input, sets the latch output to avoid a non-d...	12/02/2003
6617900	Arbitrator with no metastable voltage levels on output An arbiter that includes a phase comparator receiving two input signals. The outputs of the phase comparator are propagated to a first SR type flip-flop. The outputs of the first SR type flip-flop are propagated to a second SR type flip-flop. The outputs ...	09/09/2003
6586982	Semiconductor circuit having a combination circuit being switched between an active and inactive state A combination circuit is switched between an active state where power is supplied thereto in response to a control signal and an inactive state where power thereto is interrupted. A flip-flop circuit connected to an input terminal of the combination circu...	07/01/2003
6573774	Error correcting latch An error-correcting partial latch stage includes a first pass gate having an input for receiving a data input signal, an output, and a control node for receiving a control signal, a second pass gate having an input coupled to the output of the first pass ...	06/03/2003
6566927	Complementary pass transistor based flip-flop A complementary pass transistor based flip-flop (CP flip-flop) having a relatively small layout area and operable at a high speed with reduced power consumption is provided. The CP flip-flop does not need an additional circuit for retaining latched data i...	05/20/2003
6492857	Method and apparatus for reducing the vulnerability of latches to single event upsets A delay circuit includes a first network having an input and an output node, a second network having an input and an output, the input of the second network being coupled to the output node of the first network. The first network and the second network ar...	12/10/2002
6456136	Method and apparatus for latching data within a digital system A latching data system includes a memory element that is configured to store a data value. A latch input is coupled to the memory element, so that changes in the latch input change the data value stored in the memory element without waiting for an asserti...	09/24/2002
6452843	Method and apparatus for testing high-speed circuits based on slow-speed signals Techniques and circuits for testing high-speed circuits using slow-speed input signals. Various designs for a "stimulus" generator are provided, which is capable of generating a high-speed stimulus based on, or in response to, one or more input signals. I...	09/17/2002
6433620	Silicon-on-insulator CMOS circuit A Silicon-On-Insulator (SOI) CMOS circuit includes a plurality of PMOS transistors connected in series to each other and at least one NMOS transistor connected to one of the PMOS transistors. The NMOS transistor has its body connected to a low reference p...	08/13/2002
6424195	Dynamic flop with power down mode A dynamic flip-flop includes a first input latch coupled to receive a data input signal and a second input latch coupled to receive the complement of the data input signal. The first input latch has a first shutoff mechanism and the second input latch has...	07/23/2002
6411147	System and method for grouped gating control logic Grouped gating control logic allows for one or more inputs in a group to be active at any given time. Once an input signal in a group is active, all other pulse trains received in the same group can be locked out. Thus, by using a finite state machine to ...	06/25/2002
6407612	Method and system for suppressing input signal irregularities An input signal latching circuit for suppressing the effect of any ringing or other irregularities that occur within a specified time period after a transitional voltage level is reached, without significantly delaying the propagation of the input signal....	06/18/2002
6404254	Latch circuit and semiconductor integrated circuit having the latch circuit with control signal having a large voltage amplitude A semiconductor integrated circuit so configured to stop the supplying of an electric power to a logic circuit in a standby mode, thereby to realize a low power consumption, includes a latch circuit characterized in that as the control signal a clock sign...	06/11/2002
6373310	Scalable set/reset circuit with improved rise/fall mismatch A multiple input set/reset circuit is described that includes cross-coupled inverters connected between set and reset nodes. The set/reset circuit also includes at least one set input circuit coupled to the set node configured to receive a set signal and ...	04/16/2002
6362680	Output circuit An output circuit which can minimize the delay in combining two clocks comprises a multiplexer with a flip flop connected to one input and a clocked latch connected to the other. The clocked latch is transparent during one clocking state so that changes t...	03/26/2002
6335649	Schmitt trigger circuit A Schmitt trigger circuit of the present invention comprises a first inverter for setting a positive trigger voltage corresponding to a threshold level when an input signal is changed in a direction from a low voltage level to a high voltage level, a seco...	01/01/2002
6333662	Latch type level shift circuit A latch type level shift circuit includes an internal power supply potential generating circuit for generating first and second internal power supply potentials; a latch circuit having first and second nodes and driven by the first and second internal pow...	12/25/2001
6323710	D-type master-slave flip-flop A D-type master-slave flip-flop includes a master unit receiving an input variable and producing two first intermediate variables, a transfer unit including at least two logic gates and a clock connection connected to one input of each of the gates, which...	11/27/2001
6320441	I/O tranceiver having a pulsed latch receiver circuit A GTL I/O transceiver circuit having a pulsed latch receiver. A pulse generator generate a first pulse and a second pulse within the first pulse in response to a rising edge of the bus clock. The first pulse turns on the differential amplifier of the rece...	11/20/2001
6271701	Resetting flip-flop structures and methods for high-rate trigger generation and event monitoring D flip-flop structures are provided which respond to a DATA signal and a clock (CLK) signal by generating an output signal whose state during each clock pulse is that of the DATA signal at that pulse's leading edge and whose state between clock pulses is ...	08/07/2001
6249163	Logic circuits A transparent latch, having a signal input D, an output Q and a control input C for selecting one of two operating modes, functions by either allowing the output to follow the input (in an enable mode) or by blocking any subsequent changes in input signal...	06/19/2001
6177826	Silicon-on-insulator circuit having series connected PMOS transistors each having connected body and gate A Silicon-On-Insulator (SOI) CMOS circuit comprises a plurality of PMOS transistors connected in series to each other, each of the plurality of PMOS transistors having its body and gate connected to each other, and at least an NMOS transistor connected to...	01/23/2001
5994936	RS flip-flop with enable inputs An RS flip-flop has an inverter, connected to an input terminal of the RS flip-flop, a NOR gate having an Enable-Set input, a NAND gate having an Enable-Reset input, and a first and a second transistor connected to the inverter. The outputs of the NOR and...	11/30/1999
5952860	Amplifier using a single polarity power supply The present invention provides a power amplifier operating with a single power supply. The amplifier includes at least one depletion-mode FET for amplifying an ac signal and a negative voltage generator for providing a bias to the FET. Preferably the ampl...	09/14/1999

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Class 327/225 - With logic element (e.g., NOR gate, etc.)