Apparatus for Simulating a High Five
A self-righting hand-arm configuration which is adapted to pivot when struck by a user, thereby simulating a "high five."
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| Number | Title | Issue Date |
| 7414438 | Clock based voltage deviation detector The clock based voltage deviation detector of the present invention includes a pulse module, an indicator module and a correlation module. The pulse module generates a stream of reset pulses as a function of a clock signal. The indicator module generates a pass/fail... | 08/19/2008 |
| 7254467 | Digital train system for automatically detecting trains approaching a crossing A system for automatically detecting the presence of a train located within a detection or surveillance area of a railroad track associated with a railroad grade crossing. The system includes a transmitter unit that transmits a detection signal. The system also incl... | 08/07/2007 |
| 7242219 | Circuit for parity tree structure A circuit for a parity tree is disclosed. In one embodiment, a circuit for a parity tree includes a pull-up circuit, a pull-down circuit, and a cross-couple circuit. The circuit, an XOR/XNOR circuit, includes both an output node and an inverted output node. For a gi... | 07/10/2007 |
| 7098711 | Semiconductor device, receiver circuit, and frequency multiplier circuit A delay circuit is provided including: 2n (n is a natural number) unit delay circuits for delaying an input clock signal (with the period of T) in accordance with a delay setting signal and generating and outputting 2n phases of delayed clock signals; ... | 08/29/2006 |
| 6853218 | Multiport arbitration using phased locking arbiters An apparatus comprising a first arbiter cell, a second arbiter cell and a selection device. The first arbiter cell may be configured to lock if one or more requests are not resolved within a first predetermined time period. The second arbiter cell may be configured ... | 02/08/2005 |
| 6690203 | Method and apparatus for a failure-free synchronizer Unlike prior art synchronizers and asynchronous arbiters that produce glitches in their outputs, the present invention provides a failure-free synchronizer that can sample an arbitrary and unstable inputs while maintaining zero probability of system failu... | 02/10/2004 |
| 6674306 | Multiport arbitration using phased locking arbiters An apparatus comprising a first arbiter cell, a second arbiter cell and a selection device. The first arbiter cell may be configured to lock if one or more requests are not resolved within a first predetermined time period. The second arbiter cell may be ... | 01/06/2004 |
| 6498513 | Metastability recovery circuit An apparatus comprising an arbiter cell and a delay logic circuit. The arbiter cell may be configured to receive a plurality of request signals and provide two or more grant signals. The delay logic circuit may be configured to interface the arbiter cell ... | 12/24/2002 |
| 5875152 | Address transition detection circuit for a semiconductor memory capable of detecting narrowly spaced address changes The present invention provides a new (ATD) address transition detection circuit for use on an address bus having any number of address lines. An ATD circuit is disclosed which comprises a first and second circuit and an interval timer. The first circuit h... | 02/23/1999 |
| 5781038 | High speed phase locked loop test method and means A means and method for testing high speed phase locked loops (13) in an integrated circuit (12) at a test frequency lower than the operation speed of the phase locked loop (13). A test circuit portion (10) repeatedly tests for a zero level (42) of a recov... | 07/14/1998 |
| 5592109 | Phase comparator and PLL circuit It is an object of the present invention to provide a phase comparator which can compare phase at high speed with simple structure. The phase is compared by a precharge type NAND gate including transistors (Q35-Q37). The result of comparison in the NAND g... | 01/07/1997 |
| 5489865 | Circuit for filtering asynchronous metastability of cross-coupled logic gates A circuit is provided for filtering asynchronous metastability. The circuit includes two or more output lines that provide signals indicative of the assertion of control or data input signals at a plurality of input lines. Despite the simultaneous asserti... | 02/06/1996 |
| 4926072 | Noise elimination circuit The level of a noise removed signal which is currently delivered is compared against the level of an input signal to be detected. If the non-coincidence therebetween continues over a given time interval, the level of the noise removed signal is inverted. ... | 05/15/1990 |
| 4885544 | Determination circuit for data coincidence A coincidence determination circuit capable of reducing number of elements by providing a time period during which the coincidence determination is enabled. This coincidence determination circuit comprises, a first comparison unit provided with a pluralit... | 12/05/1989 |
| 4799023 | Circuits and apparatus which enable elimination of setup time and hold time testing errors An improved digital testing device is presented which includes the capability to detect and avoid a pair of common sources of measurement error. One source of error occurs when measurements are made within a Setup time before a transition in the signal un... | 01/17/1989 |
| 4502014 | Coincident pulse cancelling circuit A circuit responsive to pulses on first and second input signal lines for blocking the propagation of these pulses and inhibiting the production of corresponding pulses on output lines when pulses are present at the same time on the input lines and for pr... | 02/26/1985 |
| 4311962 | Variable frequency missing pulse detector A variable frequency missing pulse detector includes a reference signal generator comprising a series connected frequency-to-voltage converter and voltage-to-frequency converter which produces a reference signal with a frequency proportional to the averag... | 01/19/1982 |
| 4185210 | Contact de-bouncing circuit with common mode rejection A circuit for preventing the simultaneous application of contradictory input commands to a system and for filtering-out signals of shorter duration than a given period. The circuit includes an EXCLUSIVE-OR type gate adapted to receive input commands, whos... | 01/22/1980 |
| 4152655 | Electrical apparatus for recognizing missing pulses in an otherwise regular pulse sequence of varying frequency Omission of a pulse in an otherwise regular pulse sequence, such as may be produced by omission of a tooth of a rotating gear that is used to generate a pulse sequence through a pick-up, is utilized after the manner of a special framing pulse, saving the ... | 05/01/1979 |
| 4107616 | Signal monitoring circuit Signals such as track signals in a railway signalling system are monitored by antiphase sequential application to an enabling input of a control circuit which starts the operation of a timer, providing an output signal only if the control circuit is enabl... | 08/15/1978 |
| 4009443 | Method and apparatus for providing primary coincidence correction during particle analysis utilizing time generation techniques A method and apparatus for correcting a particle pulse count subject to coincidence error is disclosed wherein particle pulses, developed in response to passage of particles in a particulate system through a sensing zone, are counted for a predetermined p... | 02/22/1977 |
| 3984694 | Pulse width regulator for a pulsed neutron source A pulsed neutron system includes an accelerator tube having a target, an ionization section, and a replenisher for supplying accelerator gas. The power supplied to the replenisher is controlled to maintain the ionization pulse time duration within the upp... | 10/05/1976 |