Class 327/216 - JK type input

Subclass of Class 327 - Miscellaneous active electrical nonlinear devices, circuits, and systems
Definition: Subject matter wherein the multivibrator has a clock input
No. of patents: 24
Last issue date: 02/26/2008

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Number	Title	Issue Date
7336106	Phase detector and method having hysteresis characteristics A phase detector generates a first output signal if a feedback clock signal leads a reference clock signal by more than a first time. The phase detector generates a second output signal if the feedback clock signal lags the reference clock signal by more than a seco...	02/26/2008
7265599	Flipflop that can tolerate arbitrarily slow clock edges A edge triggered flipflop tolerates arbitrarily slow clock edge rates by utilizing complex gates, with weighted transistors, to electrically isolate the master latch from the data inputs, before the master latch and the slave latch are electrically connected togethe...	09/04/2007
7123069	Latch or phase detector device The invention relates to a circuit device, into which a first signal and a second signal are input, wherein a first switching array is provided, by means of which it is determined which of the two signals, is the first to change its state. The circuit device may als...	10/17/2006
6970018	Clocked cycle latch circuit A cycle latch includes a control circuit which increases the pull-up rate of a storage node by conditionally discharging the feedback node in a cross-coupled inverter keeper structure. The cycle latch includes an NMOS transistor switch for transferring an input valu...	11/29/2005
6806739	Time-borrowing N-only clocked cycle latch A cycle latch includes a control circuit which increases the pull-up rate of a storage node by conditionally discharging the feedback node in a cross-coupled inverter keeper structure. The cycle latch includes an NMOS transistor switch for transferring an input valu...	10/19/2004
6784712	Variable circuit capable of changing the connected states of its flipflops A variable circuit for constructing a desired counter by changing the circuit configuration of the connection status of a plurality of flipflops. The flipflops may be arranged in first and second rows, or stages, whereby the flipflops of the first and second rows ar...	08/31/2004
6636073	Semiconductor integrated circuit A semiconductor integrated circuit of the present invention includes MOSFETs of at least one of N channel- and P channel-types where at least two MOSFETs included in a plurality of MOSFETs, which are provided in a channel between a high potential power li...	10/21/2003
6556043	Asynchronous latch design for field programmable gate arrays A programmable logic circuit is provided that solves glitch problems associated with asynchronous logic operations associated with conventional look-up tables by utilizing a preset dominant transparent latch element to replace a conventional look-up table...	04/29/2003
6542016	Level sensitive latch A binary digital logic level sensitive latch comprising a first inverter that provides an output (O1). At least one input signal (I1) and an activation signal (Clk) are provided to the first inventer both being capacitively coupled t...	04/01/2003
6069513	Toggle flip-flop network with a reduced integration area A toggle flip-flop with reduced integration area, comprising a flip-flop of the D-type with an inverting input stage and a master-slave portion. Three transistors connected to the inverting stage form a logic gate of the XOR type whereto the output termin...	05/30/2000
5912576	Clocked register A J-K flip/flop type storage register includes an input register and an output register. The input register is active when a clock pulse applied thereto is below a predetermined level defining a logic 0 state and inactive when the clock pulse signal is ab...	06/15/1999
5532634	High-integration J-K flip-flop circuit This invention relates to a J-K flip-flop circuit which achieves a decrease in area required on an integrated circuit and a reduction of cost. Three N-MOSFETs, whose gates respectively receive a clock CL1, a J signal, and a signal from one node of a secon...	07/02/1996
5250858	Double-edge triggered memory device and system A synchronous machine uses a double-edge triggered memory cell which updates its output on both the rising and falling edges of a clock input....	10/05/1993
5045715	Circuit for generating stretched clock phases on a cycle by cycle basis A clock circuit for generating two clock signals, one (CLK) having stretched clock phases on a cycle by cycle basis, and the second (2X CLK) being a clock signal having a frequency twice the frequency of the first clock signal which is phase and edge cohe...	09/03/1991
4958090	Non-current hogging dual phase splitter TTL circuit Dual phase splitter transistor elements, an output phase splitter transistor element and a secondary phase splitter transistor element, are coupled in current mirror configuration in a TTL output buffer circuit. The output phase splitter transistor elemen...	09/18/1990
4741006	Up/down counter device with reduced number of discrete circuit elements An up/down counter device includes a D-type flip-flop circuit for producing a count signal of the 0th bit in synchronism with a clock signal, and 1st to n-th flip-flop circuits for producing count signals of the 1st to the n-th bits in synchronism with a ...	04/26/1988
4736395	Logic circuit having a test data loading function A logic circuit having a test data loading function, comprising at least one J-K flip-flop. Each J-K flip-flop includes a test data latching logic circuit. In response to an enable signal, test data is selected in place of the usual J and K input data to ...	04/05/1988
4607173	Dual-clock edge triggered flip-flop circuits A dual-clock, edge triggered, flip-flop circuit wherein one set of outputs responds to two independent inputs without giving rise to indeterminate states regardless of the combination of inputs comprising a first pair of gates (1-2 or 11-12) cross-coupled...	08/19/1986
4328435	Dynamically switchable logic block for JK/EOR functions A circuit provides either the J-K logic function or the Exclusive Or (EOR) logic function depending upon a control signal. The circuit includes a conventional cross-coupled EOR block with two inputs, the logic function being performed by the block dependi...	05/04/1982
4291241	Timing signal generating circuit A timing signal generating circuit including a clock source which generates clock pulses of a predetermined period, a binary counter which divides the frequency of the clock pulses from the clock source by n, a logical array which decodes an output of the...	09/22/1981
4230957	Logic JK flip-flop structure A logic JK flip-flop structure is disclosed which may have a dynamic, semi-dynamic or static behavior as far as the clock signal is concerned. The structure of the invention is particularly simple in design and has a minimum number of transistors although...	10/28/1980
4224534	Tri-state signal conditioning method and circuit A method and apparatus for converting a tri-state logic signal into a two-state logic signal accurately and repeatably for purposes of signal measurement. In particular, the method and apparatus deal with how the third, or high impedance state is translat...	09/23/1980
4002933	Five gate flip-flop A JK flip-flop circuit comprising four multiple input gates having each output fed back to an input to each gate of an opposite pair of said four gates; a clock pulse shaping circuit is provided when triggering clock pulses are to be of unknown shape or d...	01/11/1977
3997798	Circuit arrangement for gating out pulses and/or pulse gaps whose duration is shorter than a given test period t_p from a sequence of digital pulses present at the input end A novel circuit arrangement is provided for gating out pulses and/or pulse gaps whose duration is shorter than a given test period tp from a sequence of digital pulses present at the input end. The arrangement is such that the test period can b...	12/14/1976

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Class 327/216 - JK type input