Did You Know...
...that the Slinky toy was the result of a failed attempt by engineer Richard James to produce an antivibration device for ship instruments? His goal was to develop a spring that would instantaneously counterbalance the wave motion that rocks a ship at sea. Instead, he developed the Slinky.
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| Number | Title | Issue Date |
| 7982515 | Latch circuit tolerant to single event transient A latch circuit has: a data input unit to which an input data is input; and a data retention unit including a node connected to the data input unit. The data input unit transmits a data depending on the input data to the node, when both of a first clock signal and a... | 07/19/2011 |
| 7265582 | Level shifter A level shifter is provided. The level shifter includes a first input transistor, a second input transistor, a first bias transistor, a second bias transistor, a first switch transistor and a second switch transistor. At the time of change of the signal status, by r... | 09/04/2007 |
| 7221205 | Circuit and method for storing data in operational, diagnostic and sleep modes A clocked scan flip-flop 2 is provided in which a latch 14 within the diagnostic data path is reused to store an operational signal value during a sleep mode. The operational signal value is supplied to the latch 14 via a sleep mode path 20 | 05/22/2007 |
| 7027550 | Shift register unit and signal driving circuit using the same A shift register unit. The shift register unit outputs a shift register signal according to a clock signal, an inverse clock signal and a start signal. The shift register has first and second clock inversion circuits, and an inverter. In the first clock inversion ci... | 04/11/2006 |
| 6977529 | Differential clock signal detection circuit A semiconductor integrated circuit includes a first clock input and a second clock input to receive elements of a differential clock signal. Each clock signal element has a logic state. The circuit generates an output activation signal that depends on the states of ... | 12/20/2005 |
| 6975151 | Latch circuit having reduced input/output load memory and semiconductor chip A latch circuit to perform high-speed input and output operations by reducing a load of an input circuit or an output circuit of the latch circuit. The latch circuit includes four or more inverters connected in a loop to hold a signal, a plurality of input terminals... | 12/13/2005 |
| 6970530 | High-reliability shift register circuit The main circuit of each stage of the high-reliability shift register circuit is composed of transistors, and the turn-on time for the four transistors are only 1˜2 pulse time within one frame time. Transistors construct an inverter circuit which continuously offer... | 11/29/2005 |
| 6911845 | Pulse triggered static flip-flop having scan test A testable, pulse-triggered static flip-flop. A pulse generator produces a data enable trigger pulse only when a test enable input is low, and a scan test enable trigger pulse only when a test enable input is high. The data enable trigger pulse controls the data inp... | 06/28/2005 |
| 6822495 | System and method for implementing a skew-tolerant true-single-phase-clocking flip-flop An exemplary skew-tolerant true-single-phase-clocking (TSPC) flip-flop is disclosed that reduces current spikes by allowing willful introduction of skew in the clock tree of a single-phase circuit design. More precisely, a split-clock TSPC flip-flop, which allows th... | 11/23/2004 |
| 6742858 | Label printer-cutter with mutually exclusive printing and cutting operations A label printer-cutter includes a frame and a print head assembly connected to the frame. The print head assembly includes a print head for printing to a label media. The label printer-cutter includes a cutting assembly connected to the frame, and the cutting assemb... | 06/01/2004 |
| 6515517 | Discriminator circuit An apparatus comprising a first one or more threshold devices, a second one or more threshold devices and a logic device. The first one or more threshold devices may be configured to control an output. The second one or more threshold devices may be confi... | 02/04/2003 |
| 6510185 | Single chip CMOS transmitter/receiver A single chip RF communication system and method is provided including a transmitter and a receiver. The RF communication system in accordance with the present invention includes an antenna for receiving transmitting RF signals, a PLL for generating multi... | 01/21/2003 |
| 6486721 | Latch control circuit for crossing clock domains A latch control circuit for overcoming phase uncertainty between crossing clock domains, which includes an interface and control circuit for controlling and communicating data between the clock domains and, which also includes either static or dynamic ini... | 11/26/2002 |
| 6448829 | Low hold time statisized dynamic flip-flop A low hold time flip-flop that has a dynamic input stage and a static output stage is provided. The flip-flop uses a feedback stage to maintain a value on a dynamic node during an evaluation phase of the flip-flop so that an input to the flip-flop only ha... | 09/10/2002 |
| 6437625 | Edge triggered latch with symmetrical paths from clock to data outputs A new D-type latch structure is disclosed which has an input data sampling circuit and a symmetrical cross coupled latching circuit. The clock is delayed a predetermined time through an inverter circuit. The clock and the delayed inverted clock are used t... | 08/20/2002 |
| 6265922 | Controllable latch/register circuit A controllable latch/register circuit for an integrated circuit comprises an input latch (30) coupled in series with an output latch (32). The latches are operated under control of a control circuit (34) having mode inputs. In one mode, the latches are op... | 07/24/2001 |
| 6140855 | Dynamic-latch-receiver with self-reset pointer A dynamic latch receiver device comprises a sequence of data latch devices arranged in parallel for enabling sequential latching of data signals communicated serially on a single data line. The device includes a first pointer signal generator for generati... | 10/31/2000 |
| 6060924 | Semiconductor integrated circuit which contains scan circuits of different types A semiconductor integrated circuit includes a first shift register composed of a plurality of first flipflops each including a first selector for selecting a first or second clock, a second selector for selecting an inverted signal of the first clock or a... | 05/09/2000 |
| 6037816 | Signal transmitting circuit, signal receiving circuit, signal transmitting/receiving circuit, signal transmitting method, signal receiving method, signal transmitting/receiving method, semiconductor integrated circuit, and control method thereof In transmitting a first pair of differential clock signals UCLK, UXCLK having an extremely small amplitude voltage based on a power-source potential and a second pair of differential clock signals LCLK, LXCLK having an extremely small amplitude voltage ba... | 03/14/2000 |
| 5920089 | Multi-power supply integrated circuit and system employing the same There is disclosed a multi-power supply integrated circuit including a first pMOS transistor which is formed in a first n-well and operated at a first supply voltage and a second pMOS transistor which is formed in a second n-well and operated at a second ... | 07/06/1999 |
| 5896052 | Methods to avoid instability A multi-clock pulse synchronizer circuit with and IN-section receiving and storing prescribed in-pulses and input clock signals and responsively outputting intermediate pulses; and an OUT-section for receiving and storing the intermediate pulses, synchron... | 04/20/1999 |
| 5774003 | Flip-flop cell having clock skew protection A flip-flop cell having a main data input, a main scan data input, a main data output and a main clock input. The flip-flop cell includes a multiplexer having first and second inputs and an output. The first input is coupled to the main data input of the ... | 06/30/1998 |
| 5754070 | Metastableproof flip-flop A metastableproof flip-flop receives an input value on a flip-flop input. The flip-flop holds an output value on a flip-flop output. In response to a transition of a clock signal, a transition in the output value occurs. The new output value is the input ... | 05/19/1998 |
| 5715172 | Method for automatic clock qualifier selection in reprogrammable hardware emulation systems A method of identifying potential clock qualifiers in netlist description of an integrated circuit, the netlist comprising logic elements. The method comprises the steps of initializing every net of the netlist to a speed of zero, identifying all potentia... | 02/03/1998 |
| 5712584 | Synchronous stress test control The present invention ensures that the entire data path of the synchronous integrated circuit device composed of master and slave latches is initialized upon power-up in a test mode, thereby overcoming a prior art problem of non-initialization of the devi... | 01/27/1998 |
| 5638015 | Avoiding instability Described are techniques to stabilize storage devices receiving signals from plural asynchronous docks, especially to avoid "metastability", in particular, a multi-dock pulse synchronizer circuit with an IN-section for receiving and storing prescribed imp... | 06/10/1997 |
| 5565808 | Latch control circuit A latch, connected between an input self-reset dynamic MOS logic circuit and an output self-reset dynamic MOS logic circuit, is provided with clocked interface circuitry to assure proper latching of the state of the input logic in the latch and provides a... | 10/15/1996 |
| 5517145 | CMOS toggle flip-flop using adiabatic switching A toggle flip-flop circuit is described incorporating eight bi-directional switches which may be dual rail wherein each bi-directional switch for each rail includes an n and p channel transistor coupled in parallel. Clock input signals may have rise and f... | 05/14/1996 |
| 4743784 | Sense amplifier circuit For perfect states of balance on sense nodes, there is provided a sense amplifier circuit comprising a balancing circuit capable of establishing an electrical path between not only the sense nodes but also the sense nodes and control nodes which are opera... | 05/10/1988 |
| 4667339 | Level sensitive latch stage A logic circuit that has a plurality of stages that are driven by a clock source that provides at least 2 clock signals and includes at least a single latch stage located between two of the plurality of stages is configured with field effect transistor te... | 05/19/1987 |
| 4598214 | Low power shift register latch A combination of logic circuits perform logical operations on data and include a plurality of shift register latches. Each shift register latch includes a latch means for the storing of data, an isolation means for isolating the latch means from data and ... | 07/01/1986 |
| 4512029 | Non-volatile decade counter using Johnson code or equivalent This invention concerns counters. More specifically, it relates to a non-volatile counting decade, comprising five flipflops, the outputs of which represent the decimal contents of the decade in the Johnson code. In this code, no flipflop changes its state ... | 04/16/1985 |
| 4508980 | Sense and refresh amplifier circuit An amplifier circuit for sensing and refreshing stored information, utilized with a voltage supply. The amplifier is of the type that is capable of assuming first and second conditions in response to signals at first and second input nodes. The circuit co... | 04/02/1985 |
| 4442365 | High speed latch circuit A latch circuit has first to fourth nodes. The first node is supplied with a logic signal and the second node is charged at a first potential. A potential at the third node is discharged to the second potential. The fourth node is charged to the first pot... | 04/10/1984 |
| 4439691 | Non-inverting shift register stage in MOS technology A non-inverting integrated circuit shift register stage is provided by a combination of four interconnected N-MOS transistors, connected to a two-phase clock pulse voltage source.... | 03/27/1984 |
| 4224533 | Edge triggered flip flop with multiple clocked functions A single flip flop is integrated with MOS circuitry which enables the single flip flop to be triggered by each of several individual clocked functions without interfering with one another. The flip flop responds only to low to high transitions of each clo... | 09/23/1980 |
| 4149099 | Amplifier circuit for obtaining true and complementary output signals from an input signal An amplifier circuit for amplifying an input signal and obtaining true and complementary output signals includes cross-coupled transistors connected to first and second nodes. The first and second nodes are made to be an equal potential by precharging. Th... | 04/10/1979 |
| 4070590 | Sensing circuit for memory cells A weak signal detecting circuit in which a sensing circuit formed with a flip-flop circuit, and bit lines each having connected thereto a plurality of 1-transistor type memory cells, are interconnected by separation transistors for separating them from ea... | 01/24/1978 |
| 4051388 | Flip-flop accompanied by two current switches, one having a smaller current sink capability than the other A first current switching circuit is connected to a first node of a flip-flop circuit and has an input terminal. A second current switching circuit is connected to a second node of the flip-flop and has a control terminal connected to the first node and a... | 09/27/1977 |
| 4039861 | Cross-coupled charge transfer sense amplifier circuits Sense amplifiers employing charge-transfer techniques and cross-coupled devices for use with memory cell arrays or as comparators, polarity sensors and differential amplifiers are described which include a unique preamplifier circuit having cross-coupled ... | 08/02/1977 |
