Class 327/212 - With clock input

Subclass of Class 327 - Miscellaneous active electrical nonlinear devices, circuits, and systems
Definition: Subject matter which provides an input for a separate triggering
No. of patents: 194
Last issue date: 02/21/2012

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Number	Title	Issue Date
8120406	Sequential circuit with dynamic pulse width control A pulsed latch circuit with conditional shutoff prevents an input node, such as a node receiving data, of the pulsed latch circuit, from latching data based on a delayed input control signal, such as an internal clocking signal, and based on a feedback latch state t...	02/21/2012
7619455	Digital single event transient hardened register using adaptive hold By adjusting a register's capturing clock edge timing so that the register captures data when the data returns to a correct state, the register may be protected against DSET upsets. If a data glitch occurs near the clock edge, the valid time at the register output i...	11/17/2009
7405606	D flip-flop A D flip-flop with a reduced power product or reduced clock line capacitance is disclosed. The flip-flop includes a half-static slave stage or a master stage with clock gating by the input and output. The half-static slave stage an output inverter and a feedback ele...	07/29/2008
7365575	Gated clock logic circuit A gated clock logic circuit includes a pulse generator and a precharged latch. The pulse generator generates a pulse signal in response to a clock signal, and the precharged latch generates a gated clock signal in response to the clock signal, the pulse signal, and ...	04/29/2008
7362154	Radiation hardened latch A programmable phase frequency divider for space applications is implemented in CMOS technology, and consists of three radiation hardened D-type flip flops and combinational logic circuits to provide the feedback controls that allow programmable frequency division r...	04/22/2008
7362153	Receiver latch circuit and method In some embodiments, a receiver latch circuit, includes a dynamic latch having at least one input terminal to receive an input data signal and at least one latch terminal. The dynamic latch is adapted to generate an amplified output data signal based at least in par...	04/22/2008
7358786	Control signal generator, latch circuit, flip flop and method for controlling operations of the flip-flop A control signal generator, latch circuit, flip-flop and method for controlling operations in the flip-flop may be configured so as to efficiently perform latching and scanning operations in the flip-flop. The control signal generator may generate at least two pulse...	04/15/2008
7358787	Dual operational mode CML latch A dual purpose current mode logic (“CML”) latch circuit is provided which includes a CML latch operable to receive at least a pair of differential input data signals and at least one clock signal. The CML latch is operable to generate at least one output signal ...	04/15/2008
7320098	Semiconductor integrated circuit device having scan flip-flop circuit A semiconductor integrated circuit device has a normal operation mode and a scan test operation mode, and includes a pulse generating circuit and a scan flip-flop circuit. The pulse generating circuit generates pulse signals synchronized with a clock signal in each ...	01/15/2008
7301381	Clocked state devices including master-slave terminal transmission gates and methods of operating same A clocked state circuit can include a transmission gate configured to clock an output of a master terminal to an input of a slave terminal responsive to a clock signal or a delayed clock signal coupled to the transmission gate. ...	11/27/2007
7274235	Electronic circuitry protected against transient disturbances and method for simulating disturbances The circuitry comprises successive stages, each comprising a combinatory logic circuit connected to the input of a first latch. Staggered clock signals are respectively associated with the first latches of the odd and even stages. Means for detecting a transient dis...	09/25/2007
7265599	Flipflop that can tolerate arbitrarily slow clock edges A edge triggered flipflop tolerates arbitrarily slow clock edge rates by utilizing complex gates, with weighted transistors, to electrically isolate the master latch from the data inputs, before the master latch and the slave latch are electrically connected togethe...	09/04/2007
7265589	Independent gate control logic circuitry A dynamic logic gate has a dynamic node pre-charged in response to a pre-charge phase of a clock signal and a logic tree with a plurality of logic inputs for evaluating the dynamic node during an evaluate phase of the clock signal in response to a Boolean combinatio...	09/04/2007
7259605	Pseudo true single phase clock latch with feedback mechanism A pseudo true single phase clock latch (pseudo “TSPC” latch) includes additional circuitry coupled to three previously floating nodes that can lose data depending upon the amount of leakage current associated with these nodes. The additional circuitry, including...	08/21/2007
7256634	Elastic pipeline latch with a safe mode An elastic pipelined latch. The latch includes a control input for configuring the latch into a repeater state or a latch state, a drive component responsive to the control input and for driving an input signal through as an output signal, and a pulse width/inhibit ...	08/14/2007
7245168	Clock selection circuit and digital processing system for reducing glitches A clock selection circuit and method may operate to generate a clock signal for a digital processing system. In the clock selection circuit, first and second clock control signals may be generated based on a received control signal and/or the inverse of a received c...	07/17/2007
7212056	Radiation hardened latch A radiation hardened latch is presented. The radiation hardened latch uses two redundant inverter paths to duplicate an input signal. The duplicated inverter paths are coupled with a radiation hardened inverter that will only produce an inverted signal if both input...	05/01/2007
7180356	Semiconductor circuit The level shift circuit in the semiconductor circuit of the invention has a configuration comprising an input stage inverter circuit which inputs an input signal having a first voltage amplitude and outputs an inverted signal of this input signal, an output stage in...	02/20/2007
7167033	Data retaining circuit A data retaining circuit has been disclosed in which, even if a soft error occurs, it is corrected and a normal value can be maintained, the configuration is simple, and high-speed operations are enabled. In this circuit, when a soft error occurs in the data to be p...	01/23/2007
7167027	Latch-type level converter and receiver circuit accurately amplifying low-amplitude signals and receiving common-mode input signals higher than a supply voltage A latch-type level converter has a signal-input transistor, a latch, and a clock-input transistor. The signal-input transistor, which is a high-voltage transistor, receives an input signal, and the latch holds data of the input signal received by the signal-input tr...	01/23/2007
7161404	Single event upset hardened latch A hardened latch capable of providing protection against single event upsets (SEUs) is disclosed. The hardened latch includes a first latch and a second latch that mirrors a subset of gates of the first latch. The second latch is inserted in the feedback path of the...	01/09/2007
7151395	Data retaining circuit A data retaining circuit has been disclosed in which, even if a soft error occurs, it is corrected and a normal value can be maintained, the configuration is simple, and high-speed operations are enabled. In this circuit, when a soft error occurs in the data to be p...	12/19/2006
7132871	Data retaining circuit A data retaining circuit has been disclosed in which, even if a soft error occurs, it is corrected and a normal value can be maintained, the configuration is simple, and high-speed operations are enabled. In this circuit, when a soft error occurs in the data to be p...	11/07/2006
7132870	Differential register slave structure A differential register slave structure is presented. In one embodiment, a differential register includes a storage node (218, 318). The storage node (218, 318) stores and holds the differential values generated by the differential register. In one emb...	11/07/2006
7129767	Methods of manufacture for a low control voltage switch A low control voltage switch utilizing a plurality of field effect transistors (FETs) having a total of six gates to allow the switch to operate at a low control voltage without the need to increase device periphery or die size. Feed-forward capacitors connected bet...	10/31/2006
7109771	Semiconductor integrated circuit with reduced leakage current A combination circuit is switched between an active state where power is supplied thereto in response to a control signal and an inactive state where power thereto is interrupted. A flip-flop circuit connected to an input terminal of the combination circuit stores a...	09/19/2006
7091756	Integrated circuit A frequency divider circuit is provided having an even number of amplifier stages connected in series with the output of the last amplifier stage connected to the input of the first amplifier stage; and modulating means responsive to an input signal to be frequency ...	08/15/2006
7088161	Semiconductor integrated circuit with reduced leakage current A combination circuit is switched between an active state where power is supplied thereto in response to a control signal and an inactive state where power thereto is interrupted. A flip-flop circuit connected to an input terminal of the combination circuit stores a...	08/08/2006
7084683	High-speed differential flip-flop with common-mode stabilization A differential flip-flop (400) has an output stage (402) with first and second input terminals (X1, X2), first and second output terminals (Q, Qb), a first voltage supply terminal (Vss), a first transistor (435) having a first curr...	08/01/2006
7078939	Latch-type level converter and receiver circuit accurately amplifying low-amplitude signals and receiving common-mode input signals higher than a supply voltage A latch-type level converter has a signal-input transistor, a latch, and a clock-input transistor. The signal-input transistor, which is a high-voltage transistor, receives an input signal, and the latch holds data of the input signal received by the signal-input tr...	07/18/2006
7042249	Method for actuating a transistor The present invention provides a method for actuating a transistor (10) having the following steps: (a) a first predetermined positive potential is applied to a first voltage supply node (13) in a latch circuit (11), the voltage supply node (...	05/09/2006
7023255	Latch with data jitter free clock load A digital latch includes a latch circuit having first and second data inputs, first and second data outputs, and a clock signal input. The latch circuit has a first load value relative to a clock driver when data at the first and second data inputs is non-changing. ...	04/04/2006
6975151	Latch circuit having reduced input/output load memory and semiconductor chip A latch circuit to perform high-speed input and output operations by reducing a load of an input circuit or an output circuit of the latch circuit. The latch circuit includes four or more inverters connected in a loop to hold a signal, a plurality of input terminals...	12/13/2005
6967505	Input circuit An input circuit includes a data input unit for receiving input data of the input circuit. A data latch unit latches output data of the input circuit. A reset unit resets the data latch unit in response to a first logic level of a first clock signal. A latch enhance...	11/22/2005
6958629	Single stage, level restore circuit with mixed signal inputs A circuit comprises a signal trace to receive a first large signal, a first plurality of signal traces to receive a small signal pair and a clock trace to receive a clock signal. The circuit further comprises a mixed signal circuit having at least a first and a seco...	10/25/2005
6956405	Teacher-pupil flip-flop A teacher-pupil flip-flop with reduced register delay including a gate circuit, a stack circuit, a keeper circuit, a teacher output circuit, a latch circuit and a pupil output circuit. The gate circuit switches after a setup delay in response to transitions of a clo...	10/18/2005
6943605	Scan cell designs for a double-edge-triggered flip-flop According to some embodiments, scan cell designs are provided for a double-edge-triggered flip-flop. ...	09/13/2005
6937080	Current-controlled CMOS logic family Various circuit techniques for implementing ultra high speed circuits use current-controlled CMOS (C3MOS) logic fabricated in conventional CMOS process technology. An entire family of logic elements including inverter/buffers, level shifters, NAND, NOR, X...	08/30/2005
6924683	Edge accelerated sense amplifier flip-flop with high fanout drive capability Flip-flop devices provide fast clock-to-Q timing that exploits the pulsed nature of outputs generated by a clocked sense amplifier. These flip-flop devices include an output stage, which has a PMOS pull-up transistor and an NMOS pull-down transistor therein, and a c...	08/02/2005
6922094	Data retaining circuit A data retaining circuit has been disclosed in which, even if a soft error occurs, it is corrected and a normal value can be maintained, the configuration is simple, and high-speed operations are enabled. In this circuit, when a soft error occurs in the data to be p...	07/26/2005

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Class 327/212 - With clock input