Did You Know...
...that to encourage use of his new invention, the shopping cart, market owner Sylvan Goldman hired fake shoppers to push the carts around his store in Oklahoma City? Seems his customers were reluctant to give up their hand-carried baskets.
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| Number | Title | Issue Date |
| 8416002 | Flip-flop circuit design A flip-flop circuit includes a precharge circuit that outputs a charge signal high when a received clock signal is LOW. A delay clock input circuit generates a delayed clock input controlled signal with the same value as an input signal when the clock signal is HIGH... | 04/09/2013 |
| 8169246 | Dynamic-to-static converter latch with glitch suppression A latch circuit. The latch circuit may include an input circuit, a precharge circuit, and a transfer circuit. The precharge circuit may precharge a first node during a first phase of a clock signal. Based on an input signal received at a first logic value, the input... | 05/01/2012 |
| 8067970 | Multi-write memory circuit with a data input and a clock input Various types of memory circuits are described. A memory circuit may include a state-storage feedback loop coupled to a clock input and to a data input. The data input is introduced into the feedback loop at multiple points, and propagated in parallel from those poi... | 11/29/2011 |
| 8067971 | Providing additional inputs to a latch circuit A latch circuit for retaining and transmitting an input data value is disclosed, along with a memory, and a method for retaining and transmitting data. The latch circuit includes a primary input for receiving a data value, an output for outputting the data value, a ... | 11/29/2011 |
| 7924078 | Bistable circuit with auto-time-adjusted switching, and flip-flop using such a bistable circuit Bistable circuit switching at the edges of a clock signal, including means for pre-charging an intermediate node of the circuit, delay means including a chain of inverters defining a time window around an edge of said clock signal, means for discharging the intermed... | 04/12/2011 |
| 7782108 | Flip-flop device and method for storing and outputting a data value A flip-flop device for storing and outputting a data value includes a controllable memory element configured to be open as a function of a control pulse, a feedback means for comparing a data value present at the memory element and the data value output by the memor... | 08/24/2010 |
| 7495493 | Circuitry for latching Circuitry for latching receives an input signal and a control signal and provides an output signal. In one embodiment, the setup time (t(SL) and t(SH)) of the input signal with reference to the control signal is to the first edge of the control signal, the holding t... | 02/24/2009 |
| 7437800 | Clock gating circuit Clock gating circuits are disclosed in the present disclosure. Also disclosed herein are methods for designing clock gating circuits in the early stages of manufacturing. In one embodiment of a method for designing a clock gating circuit, the method comprises provid... | 10/21/2008 |
| 7427884 | Semiconductor device A shift register capable of supplying only a necessary clock signal to a necessary unit register with simple constitution. A semiconductor device is provided with a shift register in which a plurality of stages of unit registers is connected, in which the unit regis... | 09/23/2008 |
| 7411425 | Method for power consumption reduction in a limited-switch dynamic logic (LSDL) circuit A method for power consumption reduction in a limited-switch dynamic logic (LSDL) circuit provides reduced power consumption by reducing clock power dissipation. By clocking LSDL gates with a clock signal having a reduced voltage swing in the evaluation phase, the L... | 08/12/2008 |
| 7405606 | D flip-flop A D flip-flop with a reduced power product or reduced clock line capacitance is disclosed. The flip-flop includes a half-static slave stage or a master stage with clock gating by the input and output. The half-static slave stage an output inverter and a feedback ele... | 07/29/2008 |
| 7391250 | Data retention cell and data retention method based on clock-gating and feedback mechanism For retaining an output data signal of a data retention cell in a power-saving mode, a slave latch unit of the data retention cell is powered with a real power for preserving the output data signal. The output data signal is furnished backward to an input control ci... | 06/24/2008 |
| 7388416 | Latch circuit, 4-phase clock generator, and receiving circuit A latch circuit includes a voltage driven type data reading unit and a voltage driven type data holding unit, and operates based on a clock signal that is supplied from an outside source. The data reading unit reads both a first input data and a second input data, a... | 06/17/2008 |
| 7368970 | Level shifter circuit A level shifter circuit includes a level shifter unit and a latch unit. The level shifter unit receives two complementary input signals and converts the voltage levels of two complementary input signals. The latch unit latches the state of two output nodes before th... | 05/06/2008 |
| 7365575 | Gated clock logic circuit A gated clock logic circuit includes a pulse generator and a precharged latch. The pulse generator generates a pulse signal in response to a clock signal, and the precharged latch generates a gated clock signal in response to the clock signal, the pulse signal, and ... | 04/29/2008 |
| 7362154 | Radiation hardened latch A programmable phase frequency divider for space applications is implemented in CMOS technology, and consists of three radiation hardened D-type flip flops and combinational logic circuits to provide the feedback controls that allow programmable frequency division r... | 04/22/2008 |
| 7358787 | Dual operational mode CML latch A dual purpose current mode logic (“CML”) latch circuit is provided which includes a CML latch operable to receive at least a pair of differential input data signals and at least one clock signal. The CML latch is operable to generate at least one output signal ... | 04/15/2008 |
| 7358786 | Control signal generator, latch circuit, flip flop and method for controlling operations of the flip-flop A control signal generator, latch circuit, flip-flop and method for controlling operations in the flip-flop may be configured so as to efficiently perform latching and scanning operations in the flip-flop. The control signal generator may generate at least two pulse... | 04/15/2008 |
| 7342429 | Programmable low-power high-frequency divider Several latch circuits including a NAND gate stage and combinations of clocked inverter stages and inverter stages are described. A programmable frequency divider including homologue frequency divider circuits using the latch circuits is also described. Also describ... | 03/11/2008 |
| 7323920 | Soft-error rate improvement in a latch using low-pass filtering In a preferred embodiment, the invention provides a circuit and method for reducing soft error events in latches. A low-pass filter is placed between the output of a forward inverter and the inputs of a feedback keeper. The first and second outputs of the low-pass f... | 01/29/2008 |
| 7323911 | Differential sense amplifier circuit and method triggered by a clock signal through a switch circuit A differential sense amplifier is described that can be configured as a preamplifier or a latch circuit as triggered by a clock signal connected to a switch circuit. When the clock signal is set at a first signal level, the switch circuit in the differential sense a... | 01/29/2008 |
| 7315191 | Digital storage element architecture comprising dual scan clocks and reset functionality A digital storage element comprising a master transparent latch that receives functional data from a data input port and scan data from a scan input port and comprises a master feedback loop with a first transistor coupled to the master feedback loop. The first tran... | 01/01/2008 |
| 7304508 | Method and apparatus for fast flip-flop Embodiments related to fast flip-flops are disclosed. ... | 12/04/2007 |
| 7301381 | Clocked state devices including master-slave terminal transmission gates and methods of operating same A clocked state circuit can include a transmission gate configured to clock an output of a master terminal to an input of a slave terminal responsive to a clock signal or a delayed clock signal coupled to the transmission gate. ... | 11/27/2007 |
| 7265599 | Flipflop that can tolerate arbitrarily slow clock edges A edge triggered flipflop tolerates arbitrarily slow clock edge rates by utilizing complex gates, with weighted transistors, to electrically isolate the master latch from the data inputs, before the master latch and the slave latch are electrically connected togethe... | 09/04/2007 |
| 7265582 | Level shifter A level shifter is provided. The level shifter includes a first input transistor, a second input transistor, a first bias transistor, a second bias transistor, a first switch transistor and a second switch transistor. At the time of change of the signal status, by r... | 09/04/2007 |
| 7265589 | Independent gate control logic circuitry A dynamic logic gate has a dynamic node pre-charged in response to a pre-charge phase of a clock signal and a logic tree with a plurality of logic inputs for evaluating the dynamic node during an evaluate phase of the clock signal in response to a Boolean combinatio... | 09/04/2007 |
| 7259605 | Pseudo true single phase clock latch with feedback mechanism A pseudo true single phase clock latch (pseudo “TSPC” latch) includes additional circuitry coupled to three previously floating nodes that can lose data depending upon the amount of leakage current associated with these nodes. The additional circuitry, including... | 08/21/2007 |
| 7242235 | Dual data rate flip-flop A flip-flop is configured to operate either in a double data-rate mode or a normal mode. When configured to operate in the double data-rate mode, the flip-flop outputs data on both edges of the applied clock. When configured to operate in the normal mode, the flip-f... | 07/10/2007 |
| 7231569 | Scan flip-flop circuit with reduced power consumption A scan flip-flop circuit and related scan chain are disclosed. The scan flip flop comprises in one embodiment an input stage receiving, selecting between, and outputting either a normal logic signal or a scan logic signal in accordance with an operation mode for the... | 06/12/2007 |
| 7224197 | Flip-flop implemented with metal-oxide semiconductors using a single low-voltage power supply and control method thereof The present invention discloses a flip-flop implemented with metal-oxide semiconductors using a single low-voltage power supply and a control method thereof, wherein an external control signal is input to a power switch in order to turn on the power switch for an ac... | 05/29/2007 |
| 7221188 | Logic circuitry A logic circuit including at least one evaluate circuit coupled to a static output logic circuit. In one example, the evaluate circuit includes a dynamic node, a full keeper, an evaluate device, and a logic tree. In some examples, the output logic circuit is a sampl... | 05/22/2007 |
| 7212056 | Radiation hardened latch A radiation hardened latch is presented. The radiation hardened latch uses two redundant inverter paths to duplicate an input signal. The duplicated inverter paths are coupled with a radiation hardened inverter that will only produce an inverted signal if both input... | 05/01/2007 |
| 7202705 | Dynamic logic circuit apparatus and method for reducing leakage power consumption via separate clock and output stage control A dynamic logic circuit apparatus and method for reducing leakage power consumption via separate clock and output stage control reduces power consumption of processors and other systems incorporating dynamic circuits. The power control signal may be a delayed versio... | 04/10/2007 |
| 7196552 | Comparator circuit with offset cancellation A method of comparing signals includes obtaining first and second signals to be compared and first and second offset cancellation signals, combining the first offset cancellation signal with the first signal to be compared to form a first combined signal and combini... | 03/27/2007 |
| 7193446 | Dynamic logic circuit incorporating reduced leakage state-retaining devices A dynamic logic circuit incorporating reduced leakage state-retaining devices reduces power consumption of processors and other systems incorporating dynamic circuits. A keeper circuit provides a low leakage retention of the state of the output stage of the dynamic ... | 03/20/2007 |
| 7193406 | Data transmitting and receiving apparatus In a TEDS system, a data transmitting and receiving apparatus is provided and a signal transmitted from a TEDS memory to an apparatus side is logically inverted without using a transformer, and further a sneak signal is prevented. Inverters 28, 30 and ... | 03/20/2007 |
| 7180350 | Hybrid latch flip-flop A hybrid latch flip-flop is applied to an LCD. The hybrid latch flip-flop includes a positive pulse generation unit, a latch flip-flop, and a buffer unit. The latch flip-flop includes a sampling unit and a hold unit. One feature of the present invention is that fewe... | 02/20/2007 |
| 7180351 | Hybrid latch flip-flop A hybrid latch flip-flop is applied to an LCD. The hybrid latch flip-flop includes a negative pulse generation unit, a latch flip-flop, and a buffer unit. The latch flip-flop includes a sampling unit and a hold unit. One feature of the present invention is that fewe... | 02/20/2007 |
| 7180792 | Efficient latch array initialization An efficient method and electronic circuit for initializing latch arrays in an electronic device including an FPGA and a memory device includes a group of one or more data latches, each including a pair of cross-coupled inverting logic elements, characterized in tha... | 02/20/2007 |
